PLL130-08

PLL130-08 High Speed Translator Buffer to PECL FEATURES Differential PECL output Single AC coupled input (min. 100mV swing). Input range from DC to 1.0 GHz. 2.5V to 3.3V operation. Available in 8-Pin SOIC or 3x3mm QFN. PIN CONFIGURATION (TOP VIEW) GND REF_IN GND PECL 1 2 3 4 8 7 6 5 VDD GND PECL_BAR VDD PLL130-08 www.DataSheet4U.com DESCRIPTION The PLL130-08 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.0GHz. It provides a pair of differential PECL output. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for conversion from sine wave, TTL, CMOS, or LVDS to PECL. GND GND GND OE^ 13 14 15 16 12 11 10 GND 9 VDD VDD VDD 8 7 6 5 PECL_BAR VDD PECL GND PLL130-08 1 2 3 4 GND GND Note: ^ denotes internal pull up BLOCK DIAGRAM REF_IN Input Amplifier PECL_BAR PECL 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1 REF_IN GND PLL130-08 High Speed Translator Buffer to PECL PIN DESCRIPTIONS Name GND VDD REF_IN www.DataSheet4U.com 8pin SOIC Pin number 1,3,7 5,8 2 4 7 N/A 3x3mm QFN Pin number 1,2,4,5, 9,13,14,15 7,10,11,12 3 6 8 16 Type P P I O O I Ground. Description PECL PECL_BAR OE Power supply. Reference input signal. The frequency of this signal will be reproduced at the output (after translation to PECL level). PECL True output. PECL Complementary output. Output enable (...