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PLL103-03 Dataheets PDF



Part Number PLL103-03
Manufacturers PhaseLink Corporation
Logo PhaseLink Corporation
Description DDR SDRAM Buffer
Datasheet PLL103-03 DatasheetPLL103-03 Datasheet (PDF)

Preliminary PLL103-03 DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS FEATURES Generates 24-output buffers from one input. Supports up to 4 DDR DIMMS or 3 SDR DIMMS and 2 DDR DIMMS. • Supports 266MHz DDR SDRAM. • One additional output for feedback. • Less than 5ns delay. • Skew between any outputs is less than 100 ps. www.DataSheet4U.com • 2.5V or 3.3V Supply range. • Enhanced DDR and SDRAM Output Drive selected by I2C. • Available in 48 pin SSOP. • • PIN CONFIGURATION FBOUT VDD3.3_2.5 GND D.

  PLL103-03   PLL103-03


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Preliminary PLL103-03 DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS FEATURES Generates 24-output buffers from one input. Supports up to 4 DDR DIMMS or 3 SDR DIMMS and 2 DDR DIMMS. • Supports 266MHz DDR SDRAM. • One additional output for feedback. • Less than 5ns delay. • Skew between any outputs is less than 100 ps. www.DataSheet4U.com • 2.5V or 3.3V Supply range. • Enhanced DDR and SDRAM Output Drive selected by I2C. • Available in 48 pin SSOP. • • PIN CONFIGURATION FBOUT VDD3.3_2.5 GND DDR0T_SDRAM10 DDR0C_SDRAM11 DDR1T_SDRAM0 DDR1C_SDRAM1 VDD3.3_2.5 GND DDR2T_SDRAM2 DDR2C_SDRAM3 VDD3.3_2.5 BUF_IN GND DDR3T_SDRAM4 DDR3C_SDRAM5 VDD3.3_2.5 GND DDR4T_SDRAM6 DDR4C_SDRAM7 DDR5T_SDRAM8 DDR5C_SDRAM9 DDR0T_SDRAM10 1 2 3 4 5 6 7 8 48 47 46 45 44 43 42 41 SEL_DDR VDD2.5 GND DDR11T DDR11C DDR10T DDR10C VDD2.5 GND DDR9T DDR9C VDD2.5 PD# GND DDR8T DDR8C VDD2.5 GND DDR7T DDR7C DDR6T DDR6C GND SCLK PLL103-03 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 BLOCK DIAGRAM VDD3.3_2.5 SDATA SDATA SCLK I2C Control DDR0C_SDRAM11 DDR1T_SDRAM0 DDR1C_SDRAM1 DDR2T_SDRAM2 DDR2C_SDRAM3 DDR3T_SDRAM4 DDR3C_SDRAM5 DDR4T_SDRAM6 Note: #: Active Low DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-03 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 266 chipset. The PLL103-03 also has an I2C interface, which can enable or disable each output clock. When power up, all output clocks are enabled (has internal pull up). BUF_IN DDR4C_SDRAM7 DDR5T_SDRAM8 DDR5C_SDRAM9 DDR6T DDR6C DDR7T DDR7C DDR8T DDR8C DDR9T DDR9C DDR10T DDR10C DDR11T DDR11C PD# FBOUT 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 08/28/00 Page 1 Preliminary PLL103-03 DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS PIN DESCRIPTIONS Name FBOUT BUF_IN PD www.DataSheet4U.com Number 1 13 36 Type O I I Description Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V. Reference input from chipset. 3.3V input for STANDARD SDRAM mode; 2.5V input for DDR-ONLY mode. Power Down Control input. When low, it will tri-state all outputs. SEL_DDR 48 I Input configure for DDR-ONLY mode or STANDARD SDR mode. 1 = DDR-ONLY mode (when VDD3.3_2.5 select 2.5V); 0 = SDR mode (when VDD3.3_2.5 select 3.3V). In DDR-ONLY mode, all outputs will be configured as DDR outputs. In STANDARD SDR mode, pin 4, 5, 6, 7, 10, 11, 15, 16, 19, 20, 21 and 22 will be configured as STANDARD SDR outputs, and pin 27, 28, 29, 30, 33, 34, 38, 39, 42, 43, 44 and 45 will be configured as DDR outputs. These outputs provide True copies of BUF_IN. These outputs provide complementary copies of BUF_IN. When SEL_DDR=1, these outputs provide DDR mode outputs; when SEL_DDR=0, these outputs provide standard SDRAM mode outputs. Voltage swing depends on VDD3.3_2.5. When SEL_DDR=1, these outputs provide complementary copies of BUF_IN; when SEL_DDR=0, these outputs provide standard SDRAM mode outputs. Voltage swing depends on VDD3.3_2.5. When VDD=2.5V, SEL_DDR=1. DDR-ONLY mode is selected; when VDD=3.3V, SEL_DDR=0. STANDARD SDRAM mode is selected. 2.5V power supply. Ground. DDR[6:11]T DDR[6:11]C DDR[0,1:5]T_SDRA M [10,0,2,4,6,8] DDR[0,1:5]C_SDRA M [11,1,3,5,7,9] VDD3.3_2.5 VDD2.5 GND 28,30,34, 39,43,45 27,29,33, 38,42,44 4,6,10,15,19 , 21 5,7,11,16,20 , 22 2,8,12,17,23 32,37,41,47 3,9,14,18,26 , 31,35,40,46 O O O O P P P 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 08/28/00 Page 2 Preliminary PLL103-03 DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS I2C BUS CONFIGURATION SETTING Address Assignment Slave Receiver/Transmitter Data Transfer Rate www.DataSheet4U.com A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W _ Provides both slave write and readback functionality Standard mode at 100kbits/s This serial protocol is designed to allow both blocks write and read from the controller. The bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will terminate the transfer. The write or read block both begins with the master sending a slave address and a write condition (0xD2) or a read condition (0xD3). Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte Count Byte will be read by the master then all other Data Byte . Byte Count Byte default at power-up is = (0x09). Data Protocol I2C CONTROL REGISTERS 1. BYTE 6: Outputs Register (1=Enable, 0=Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 48 4.


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