PLL102-15

PLL102-15 Low Skew Output Buffer FEATURES Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation). Zero input - output delay. Less than 700 ps device - device skew. Less than 250 ps skew between outputs. www.DataSheet4U.com Less than 200 ps cycle - cycle jitter. Output Enable function tri -state outputs. 3.3V operation. Available in 8 -Pin 150mil SOIC. PIN CONFIGURATION VDD CLK1 CLKOUT GND 1 2 3 4 8 7 6 5 N/C CLK3 CLK2 REF_IN PLL102-15 Remark If REF_IN clock is stopped for more than 10us after it has already been provided to the chip, and after power-up, the output clocks will disappear. In that instance, a full power-up reset is required in order to reactivate the output clocks. DESCRIPTIONS The PLL102 -15 is a high performance, low skew, low jitter zero delay buffer designed to di stribute high speed clocks and is available in 8 -pin SOIC or TSSOP package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feedback to the input of the PLL. Since the skew b etween the input and outpu t is less than ±350 ps, the device acts as a zero delay buffer. BLOCK DIAGRAM REF_IN PLL CLKOUT CLK1 CLK2 CLK3 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/06/03 Page 1 PLL102-15 Low Skew Output Buffer PIN DESCRIPTIONS Name VDD CLK1 3 CLKOUT 3 GND www.DataS...