PECL_RX

ANALOG IP BLOCK PECL_RX - CMOS PECL Receiver DATA SHEET PROCESS C35B3 (0.35um) DESCRIPTION The PECL_RX is a 3.3 V PECL differential line receiver featuring an operating frequency up to 311 MHz (622 Mb/s) and accepting standard F100K levels (referred to the positive supply). The PECL_RX accepts (750 mV) differential input signals and translates them to CMOS output levels. With the companion line driver (PECL_TX ) it can be used for high speed applications. The cell PECL_RX requires the PERXBIAS cell for biasing. PERXBIAS can drive up to 3 PECL_RX cells. An external voltage reference must be used. The PECL_RX can be set in power down mode. www.DataSheet4U.com FEATURES ! ! ! ! ! ! ! ! ! PECL_RX area: 0.1 mm2, size: x = 300 µm y = 340 µm PERXBIAS size: x = 382 µm y = 375 µm 3.3 V ±10% supply voltage 622 Mb/s transmission speed 1 ns max. propagation delay Power dissipation 23 mW at 3.3 V static without PERXBIAS Junction temperature –40 - 125°C Output levels fully compatible with F100K PECL Family Power down mode Revision B, 10.09.02 Page 1 of 6 Datasheet: PECL_RX - C35 TECHNICAL DATA FOR PECL_RX (Tjunction = −40 to 125 °C, VDDPECL = VDDCMOS = VDDA = +3.0 V to +3.6 V, XPD = High, SIM = Low, unless otherwise specified) DC CHARACTERISTICS Symbol VID Parameter Differential Input VID = |VINP – VINN| VICM VIH www.DataSheet4U.com Conditions Min 250 Typ 750 −1.3 Max 900 −1.1 –0.870 –1.475 100 Units mV Common Mode Input Voltage VICM = (VINP + VINN) / 2 Input Voltage High In...