MTP75N03HDL

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTP75N03HDL/D Advanced Information HDTMOS E-FET ™ High Density Power FET N–Channel Enhancement–Mode Silicon Gate This advanced high–cell density HDTMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low–voltage, high–speed switching applications in power supplies, converters and PWM motor controls, and inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs www.DataSheet4U.com where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on), High–Cell Density, HDTMOS SPICE Parameters Available Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Avalanche Energy Specified MTP75N03HDL Motorola Preferred Device TMOS POWER FET LOGIC LEVEL 75 AMPERES RDS(on) = 9.0 mOHM 25 VOLTS ™ D G S CASE 221A–06, Style 5 TO–220AB MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain–Source Voltage Drain–Gate Voltage (RGS = 1.0 MΩ) Gate–Source Voltage — Continuous Gate–Source Voltage — Single Pulse (tp ≤ 10 ms) Drain Current — Continuous — Continuous @ 100°C — Single Pulse (tp ≤ 10 µs) Total Power Dissipation Derate above 25°C Operating and Storage Temperature Range Single Pulse Drain–to–Source Avalanche Ene...