HY5PS561621LF

HY5PS56421(L)F HY5PS56821(L)F HY5PS561621(L)F www.DataSheet4U.com 256Mb DDR2 SDRAM HY5PS56421(L)F HY5PS56821(L)F HY5PS561621(L)F This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0/ July. 2004 1 HY5PS56421(L)F HY5PS56821(L)F HY5PS561621(L)F Revision History Rev. 0.1 0.2 0.3 www.DataSheet4U.com1.0 History Initial Release Editorial clean up, changed tRAS spec. for DDR2 400 1) Defined IDD Spec. 2) Added Speed bins table in AC timming specification Transfered Functional description, command truth table pages and Some contents of Operating conditions to Draft Date Dec. 2003 Jan. 2004 May 2004 Jul. 2004 Rev 1.0/July. 2004 2 HY5PS56421(L)F HY5PS56821(L)F HY5PS561621(L)F Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Feaures 1.1.2 Ordering Information 1.1.3 Ordering Frequency 1.2 Pin configuration 1.3 Pin Description www.DataSheet4U.com 2. Maximum DC ratings 2.1 Absolute Maximum DC Ratings 2.2 Operating Temperature Condition 3. AC & DC Operating Conditions 3.1 DC Operating Conditions 5.1.1 Recommended DC Operating Conditions(SSTL_1.8) 5.1.2 ODT DC Electrical Characteristics 3.2 DC & AC Logic Input Levels 3.2.1 Input DC Logic Level 3.2.2 Input AC Logic Level 3.2.3 AC Input Test Conditions 3.2.4 Differential Input AC Logic Level 3.2.5 Differential AC ...