DAPDNA-2

www.DataSheet4U.com DAPDNA-2 A Dynamically Reconfigurable Processor with 376 32-bit Processing Elements Tomoyoshi Sato Vice President & CTO IPFlex Inc. HotChips17 16 Aug 2005 Agenda          Overview Design Goals and Decisions Overall Architecture Processing Element (PE) Architecture Interconnect Architecture Application Construction Performance Advanced Usages Summary HotChips 17 16 Aug 2005 <2 > www.DataSheet4U.com DAPDNA-2      32bit RISC + Reconfigurable Fabric + Peripherals Fujitsu 0.11µm 7Cu+1Al 12 M gates 1156-pin FCBGA, 2.4V I/O, 1.2V Core 166 MHz, 3-7 W www.DataSheet4U.com  Suited for stream processing  10-50x performance of 3GHz general-purpose CPU HotChips 17 16 Aug 2005 <3 > Design Goals and Decisions  High performance Massively parallel processing elements www.DataSheet4U.com  Flexibility Field programmable  Versatility Dynamically reconfigurable with small overhead  Ease of use Fixed-frequency coarse-grained ALUs  Scalability High-bandwidth I/O (interconnect) channels HotChips 17 16 Aug 2005 <4 > DAPDNA-2 Architecture  CPU for sequential tasks DAP (Digital Application Processor) 32-bit RISC with 2way 8k+8k I/D caches www.DataSheet4U.com  Reconfigurable fabric for parallel processing DNA (Distributed Network Architecture)      376 heterogeneous 32-bit processing elements ALUs, RAMs, delays, counters, I/O buffers 4 configuration banks: switchable in one cycle 28 billion ALU operations / s (166MHz x 168) 9 billion 16x1...