Document
IDTTM InterpriseTM Integrated Communications Processor
79RC32435
Device Overview
The 79RC32435 is a member of the IDT™ Interprise™ family of PCI integrated communications processors. It incorporates a high performance CPU core and a number of on-chip peripherals. The integrated processor is designed to transfer information from I/O modules to main memory with minimal CPU intervention, using a highly sophisticated direct memory access (DMA) engine. All data transfers through the RC32435 are achieved by writing data from an on-chip I/O peripheral to main memory and then out to another I/O module.
Features
x 32-bit CPU Core – MIPS32 instruction set – Cache Sizes: 8KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches – 16 dual-entry JTLB with variable page sizes – 3-entry instruction TLB – 3-entry data TLB – Max issue rate of one 32x16 multiply per clock – Max issue rate of one 32x32 multiply every other clock – CPU control with start, stop, and single stepping – Software breakpoints support – Hardware breakpoints on virtual addresses – ICE Interface that is compatible with v2.5 of the EJTAG Specification
x PCI Interface – 32-bit PCI revision 2.2 compliant – Supports host or satellite operation in both master and target modes – Support for synchronous and asynchronous operation – PCI clock supports frequencies from 16 MHz to 66 MHz – PCI arbiter in Host mode: supports 6 external masters, fixed priority or round robin arbitration – I2O “like” PCI Messaging Unit
x Ethernet Interface – 10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant – Supports MII or RMII PHY interface – Supports 64 entry hash table based multicast address filtering – 512 byte transmit and receive FIFOs – Supports flow control functions outlined in IEEE Std. 802.3x1997
x DDR Memory Controller – Supports up to 256MB of DDR SDRAM – 1 chip select supporting 4 internal DDR banks – Supports a 16-bit wide data port using x8 or x16 bit wide DDR SDRAM devices – Supports 64 Mb, 128 Mb, 256 Mb, 512 Mb, and 1Gb DDR SDRAM devices – Data bus multiplexing support allows interfacing to standard DDR DIMMs and SODIMMs – Automatic refresh generation
Block Diagram
ICE DDR (16-bit)
MIPS-32 CPU Core
EJTAG D. Cache
MMU I. Cache
PMBus DDR Controllers
MII/RMII
Interrupt Controller
: :
3 Counter Timers
1 Ethernet 10/100
Interface
IPBusTM
I2C Bus
I2C Controller
NVRAM Controller
DMA Controller
Arbiter
Memory & I/O Controller
Bus/System Integrity Monitor
1 UART (16550)
GPIO Interface
SPI Controller
PCI Master/Target
Interface
PCI Arbiter (Host Mode)
Memory & Peripheral Bus (8-bit)
Serial Channel GPIO Pins SPI Bus
PCI Bus
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IDT 79RC32435
x Non-Volatile RAM – Provides 512-bits of non-volatile storage – Eliminates need for external boot configuration vector – Stores initial PCI configuration register values when PCI configured to operate in satellite mode with suspended CPU execution – Authorization unit ensures only authorized software will operate on the system
x Memory and Peripheral Device Controller – Provides “glueless” interface to standard SRAM, Flash, ROM, dual-port memory, and peripheral devices – Demultiplexed address and data buses: 8-bit data bus, 26-bit address bus, 4 chip selects, control for external data bus buffers Automatic byte gathering and scattering – Flexible protocol configuration parameters: programmable number of wait states (0 to 63), programmable postread/postwrite delay (0 to 31), supports external wait state generation, supports Intel and Motorola style peripherals – Write protect capability per chip select – Programmable bus transaction timer generates warm reset when counter expires – Supports up to 64 MB of memory per chip select
x DMA Controller – 6 DMA channels: two channels for PCI (PCI to Memory and Memory to PCI), two channels for the Ethernet interface, and two channels for memory to memory DMA operations – Provides flexible descriptor based operation – Supports unaligned transfers (i.e., source or destination address may be on any byte boundary) with arbitrary byte length
x Universal Asynchronous Receiver Transmitter (UART) – Compatible with the 16550 and 16450 UARTs – 16-byte transmit and receive buffers – Programmable baud rate generator derived from the system clock – Fully programmable serial characteristics:
– 5, 6, 7, or 8 bit characters
– Even, odd or no parity bit generation and detection
– 1, 1-1/2 or 2 stop bit generation – Line break generation and detection – False start bit detection – Internal loopback mode x I2C-Bus – Supports standard 100 Kbps mode as well as 400 Kbps fast
mode – Supports 7-bit and 10-bit addressing – Supports four modes: master transmitter, master receiver,
slave transmitter, slave receiver x Additional Gen.