79RC32K438

IDTTM InterpriseTM Integrated Communications Processor 79RC32438 Features 32-bit CPU Core – MIPS32 instruction set – Cache Sizes: 16KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches – 16 dual-entry JTLB with variable page sizes – 3-entry instruction TLB www.DataSheet4U.com – 3-entry data TLB – Max issue rate of one 32x16 multiply per clock – Max issue rate of one 32x32 multiply every other clock – CPU control with start, stop and single stepping – Software breakpoints support – Hardware breakpoints on virtual addresses – Enhanced JTAG and ICE Interface that is compatible with v2.5 of the EJTAG Specification ◆ DDR Memory Controller – Supports up to 2GB of DDR SDRAM – 2 chip selects (each chip select supports 4 internal DDR banks) – Supports 16-bit or 32-bit data bus width using 8, 16, or 32-bit devices – Supports 64Mb, 128Mb, 256Mb, 512Mb, and 1Gb DDR SDRAM devices – Data bus multiplexing support allows interfacing to standard DDR DIMMs and SODIMMs – Automatic refresh generation ◆ Memory and Peripheral Device Controller – Provides “glueless” interface to standard SRAM, Flash, ROM, dual-port memory, and peripheral devices – Demultiplexed address and data buses: 16-bit data bus, 26-bit address bus, 6 chip selects, supports alternate bus masters, control for external data bus buffers – Supports 8-bit and 16-bit width devices Automatic byte gathering and scattering – Flexible protocol configuration parameters: programmable number...