Document
STB16NM50N - STF/I16NM50N STP16NM50N - STW16NM50N
N-channel 500 V - 0.21 Ω - 15 A MDmesh™ II Power MOSFET D2PAK - I2PAK - TO-220 - TO-247- TO-220FP
Features
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Type
VDSS (@Tjmax) 550 V 550 V 550 V 550 V 550 V
RDS(on) max 0.26 Ω 0.26 Ω 0.26 Ω 0.26 Ω 0.26 Ω
ID
1
3
3 12
STB16NM50N STI16NM50N STF16NM50N STP16NM50N STW16NM50N
15 A 15 A 15 A (1)
D²PAK
2 1 3
I²PAK
15 A 15 A
3 1 2
TO-247
3 1 2
1. Limited only by maximum temperature allowed ■ ■ ■
100% avalanche tested Low input capacitance and gate charge Low gate input resistance
TO-220
TO-220FP
Figure 1.
Internal schematic diagram
Application
■
Switching applications
Description
This series of devices is designed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a new vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters.
Table 1.
Device summary
Marking B16NM50N I16NM50N F16NM50N P16NM50N W16NM50N Package D²PAK I²PAK TO-220FP TO-220 TO-247 Packaging Tape and reel Tube Tube Tube Tube
Order codes STB16NM50N STI16NM50N STF16NM50N STP16NM50N STW16NM50N
March 2008
Rev 2
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Contents
STB16NM50N - STF/I16NM50N - STP16NM50N - STW16NM50N
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................ 6
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3
Test circuit
................................................ 9
4 5 6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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STB16NM50N - STF/I16NM50N - STP16NM50N - STW16NM50N
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Value Parameter D²PAK/I²PAK TO-220FP TO-220/TO-247 500 ± 25 15 9.4 60 125 15 --55 to 150 150 2500 15 (1) 9.4 (1) 60 (1) 30 Unit
VDS
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Drain-source voltage (VGS=0) Gate-source voltage Drain current (continuous) at TC = 25°C Drain current (continuous) at TC = 100°C Drain current (pulsed) Total dissipation at TC = 25°C Peak diode recovery voltage slope Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1s;TC=25°C) Storage temperature Max. operating junction temperature
V V A A A W V/ns V °C °C
VGS ID ID IDM (2) PTOT dv/dt (3) VISO Tstg Tj
1. Limited only by maximum temperature allowed 2. Pulse width limited by safe operating area 3. ISD ≤15A, di/dt ≤400A/µs, VDD = 80% V(BR)DSS
Table 3.
Symbol
Thermal data
Value Parameter TO-220 I²PAK D²PAK TO-247 TO-220FP Thermal resistance junctioncase max Thermal resistance junctionamb max Thermal resistance junctionpcb max Maximum lead temperature for soldering purposes -62.5 -Unit
Rthj-case Rthj-amb Rthj-pcb Tl
1 -30 300 50 --
4.2 62.5 --
°C/W °C/W °C/W °C
Table 4.
Symbol IAS EAS
Avalanche characteristics
Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) Single pulse avalanche energy (starting Tj=25°C, ID=IAS, VDD= 50V) Max value 6 470 Unit A mJ
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Electrical characteristics
STB16NM50N - STF/I16NM50N - STP16NM50N - STW16NM50N
2
Electrical characteristics
(TCASE=25 °C unless otherwise specified) Table 5.
Symbol V(BR)DSS
On/off states
Parameter Drain-source breakdown voltage Drain-source voltage slope Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 1 mA, VGS= 0 VDD = 400 V,ID = 15 A, VGS = 10 V VDS = Max rating, VDS = Max rating@125 °C VGS = ±20 V VDS= VGS, ID = 250 µA VGS= 10 V, ID= 7.5 A 2 3 0.21 Min. 500 30 1 100 100 4 0.26 Typ. Max. Unit V V/ns µA µA nA V Ω
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dv/dt(1)
IDSS IGSS VGS(th) RDS(on)
1.
Characteristics value at turn off on inductive load
Table 6.
Symbol gfs(1) Ciss Coss Crss Coss eq.(2)
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Equivalent output capacitance Gate input resistance Test conditions VDS =15 V, ID= 7.5 A VDS = 50 V, f =1 MHz, VGS = 0 Min. Typ. 10 1200 80 10 170 Max. Unit S pF pF pF pF
VGS = 0, VDS = 0 to 400 V f=1 MHz Gate DC Bias=0 Test signal level=20 mV open drain VDD = 400 V, ID = 15 A VGS = 10 V (see Figure 19)
Rg
5
Ω nC nC nC
Qg Qgs Qgd
1.
Total gate charge Gate-source charge Gate-drain charge
38 7 19
Pulsed: pulse duration = 300µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
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STB16NM50N - STF.