March 2007
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HYB39S C12880 0 FE HYB39S C12816 0 FE HYI39SC128800FE HYI39SC128160FE
128-MBit Synchronous DRAM Green Product SDRAM
Internet Data Sheet
Rev. 1.1
Internet Data Sheet
HY[B/I]39SC128[800/160]FE 128-MBit Synchronous DRAM
HYB39SC128800FE, HYB39SC128160FE, HYI39SC128800FE, HYI39SC128160FE Revision History: 2007-02, Rev. 1.1 Page All 9 www.DataSheet4U.com 13 Subjects (major changes since last revision) Adapted internet edition Corrected block diagram Corrected mode register definition
Previous Revision: 2006-09, Rev. 1.0
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qag_techdoc_rev400 / 3.2 QAG / 2006-07-21 09072006-N4GC-EREN
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Internet Data Sheet
HY[B/I]39SC128[800/160]FE 128-MBit Synchronous DRAM
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Overview
Features
• • • • • • • • • Data Mask for Read / Write control (×8) Data Mask for Byte Control (×16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 µs) Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plastic Packages: PG–TSOPII–54 400 mil width
This chapter lists all main features of the product family HY[B/I]39S128[800/160]FE and the ordering information.
1.1
• • • • • • • • •
Fully Synchronous to Positive Clock Edge 0 to 70 °C Operating Temperature for HYB... -40 to 85 °C Operating Temperature for HYI... Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2 & 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 and full page Multiple Burst Read with Single Write Operation Automatic and Controlled Precharge Command
TABLE 1
Performance
Product Type Speed Code Speed Grade Max. Clock Frequency @CL3 –6 PC166–333 –7 PC133–222 143 7 5.4 7.5 5.4 Unit — MHz ns ns ns ns
@CL2
fCK3 tCK3 tAC3 tCK2 tAC2
166 6 5.4 7.5 5.4
1.2
Description
output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V power supply. All 128-Mbit components are available in PG– TSOPII–54 packages.
The HY[B/I]39S128[800/160]FE are four bank Synchronous DRAM’s organized as 16 MBit ×8 and 8 Mbit ×16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with Qimonda advanced 0.11 µm 128-MBit DRAM process technology. The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and
Rev. 1.1, 2007-02 09072006-N4GC-EREN
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Internet Data Sheet
HY[B/I]39SC128[800/160]FE 128-MBit Synchronous DRAM
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type HYB39SC128800FE-6
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Speed Grade PC166–333 PC133–222
Description 166MHz 16M ×SDRAM 166MHz 8M ×16 SDRAM 143MHz 16M ×8 SDRAM 143MHz 8M ×16 SDRAM
Package PG-TSOPII-54
Note
1)
Standard Operating Temperature HYB39SC128160FE-6 HYB39SC128800FE-7 HYB39SC128160FE-7 Industrial Operating Temperature HYI39SC128800FE-6 HYI39SC128160FE-6 HYI39SC128800FE-7 HYI39SC128160FE-7 PC133–222 PC166–333 166MHz 16M ×8 SDRAM 166MHz 8M ×16 SDRAM 143MHz 16M ×8 SDRAM 143MHz 8M ×16 SDRAM PG-TSOPII-54
1)
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.1, 2007-02 09072006-N4GC-EREN
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Internet Data Sheet
HY[B/I]39SC128[800/160]FE 128-MBit Synchronous DRAM
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Pin Configuration
Pin Configuration
This chapter contains the pin configuration for the ×8, ×16 organization of the SDRAM.
2.1
Listed below are the pin configurations sections for the various signals of the SDRAM.
TABLE 3
Pin Configuration of the SDRAM
Ball No. Name Pin Type I I I I I I I I I I I I I I I I I I I I Buffer Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Address Signal 9:0, Address Signal 10/Auto precharge Chip Select Bank Address Signals 1:0 Function
Clock.