NT5SV32M6CT

NT5SV32M4CT NT5SV16M8CT NT5SV8M16CT 128Mb Synchronous DRAM Features High Performance: -7K 3 CL=2 fCK tCK tAC t Clock Frequency Clock Cycle Clock Access Time1 Clock Access 2 -75B, CL=3 133 7.5 — 5.4 -8B, CL=2 100 10 — 6 Units MHz ns ns ns 133 7.5 — 5.4 AC Time www.DataSheet4U.com 1. Terminated load. See AC Characteristics on page 37. 2. Unterminated load. See AC Characteristics on page 37. 3. tRP = tRCD = 2 CKs Single Pulsed RAS Interface Fully Synchronous to Positive Clock Edge Four Banks controlled by BS0/BS1 (Bank Select) Programmable CAS Latency: 2, 3 Programmable Burst Length: 1, 2, 4, 8 Programmable Wrap: Sequential or Interleave Multiple Burst Read with Single Write Option Automatic and Controlled Precharge Command Data Mask for Read/Write control (x4, x8) Dual Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode Standard Power operation 4096 refresh cycles/64ms Random Column Address every CK (1-N Rule) Single 3.3V ± 0.3V Power Supply LVTTL compatible Package: 54-pin 400 mil TSOP-Type II Description The NT5SV32M4CT, NT5SV16M8CT, and NT5SV8M16CT are four-bank Synchronous DRAMs organized as 8Mbit x 4 I/O x 4 Bank, 4Mbit x 8 I/O x 4 Bank, and 2Mbit x 16 I/O x 4 Bank, respectively. These synchronous devices achieve high-speed data transfer rates of up to 133MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated ...