256Mb
Key Features
Double-data-rate architecture; two data transfers per clock cycle Bidirectional data strobe(DQS) Four banks operation Differential clock inputs(CK and CK) DLL aligns DQ and DQS transition with CK transition MRS cycle with address key programs -. Read latency 2, 2.5 (clock) www.DataSheet4U.com -. Burst length (2, 4, 8) -. Burst ...
