MPC951

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver The MPC950/951 are 3.3V compatible, PLL based clock driver devices targeted for high performance clock tree designs. With output frequencies of up to 180MHz and output skews of 375ps the MPC950 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycle–to–cycle and long term jitter. This parameter is of significant importance when the clock driver is providing the reference clock for PLL’s on board today’s microprocessors and ASiC’s. The devices offer 9 low skew outputs, the outputs are configurable to support the clocking needs of the various high performance microprocessors. www.DataSheet4U.com MPC950 MPC951 LOW VOLTAGE PLL CLOCK DRIVER Fully Integrated PLL Oscillator or Crystal Reference Input Output Frequency up to 180MHz Outputs Disable in High Impedance Compatible with PowerPC™, Intel and High Performance RISC Microprocessors TQFP Packaging Output Frequency Configurable ±100ps Typical Cycle–to–Cycle Jitter FA SUFFIX 32–LEAD TQFP PACKAGE CASE 873A–02 Two selectable feedback division ratios are available on the MPC950 to provide input reference clock flexibility. The FBSEL pin will choose between a divide by 8 or a divide by 16 of the VCO frequency to be compared with the input reference to the MPC950. The internal VCO is running at either 2x or 4x the high speed output, depending on configuration, so that the input refere...