MPC953

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview Low Voltage PLL Clock Driver The MPC953 is a 3.3V compatible, PLL based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 87.5MHz and output skews of 150ps the MPC953 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycle–to–cycle and phase jitter. MPC953 Fully Integrated PLL Output Frequency up to 87.5MHz www.DataSheet4U.com Outputs Disable in High Impedance TQFP Packaging 100ps Cycle–to–Cycle Jitter The MPC953 has a differential LVPECL reference input along with an external feedback input. These features make the MPC953 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will reset the internal counters and tristate the output buffers when driven “high”. If the reference clock (PECL_CLK) is lost or shut down when the MPC953 is in phase–lock, the output frquency will slew slowly downward. The final VCO frequency will be around TBDMHz. The MPC953 is fully 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS or LVTTL compatible levels while the outputs provide LVCMOS levels with the ability to drive terminated 50Ω transmission lines. For series terminated 50Ω lines, each of the MPC953 outputs can drive two traces giving the device an effective fan...