CY7C954DX

54DX CY7C954DX ATM HOTLink® Transceiver Features Second-generation HOTLink® technology UTOPIA level I and II compatible host bus interface Three-bit Multi-PHY address capability built-in Three user-selectable Start Of Cell marker/indicators Embedded 256-character synchronous FIFOs Built-in ATM Header Error Control (HEC) Automatic Transmit-HEC insertion & Receiver-HEC check www.DataSheet4U.com FIFO cell-level flushing of invalid ATM cells ATM Forum, Fibre Channel, and ESCON® compliant 8B/10B encoder/decoder 50- to 200-MBaud serial signaling rate Internal PLLs with no external PLL components Dual differential PECL-compatible serial inputs Dual differential PECL-compatible serial outputs Compatible with fiber-optic modules and copper cables Built-In Self-Test (BIST) for link testing Link Quality Indicator Single +5.0V ±10% supply 100-pin TQFP 0.35µ CMOS technology technology, functionality, and integration over the field proven CY7B923/933 HOTLink. The transmit section of the CY7C954DX HOTLink has been configured to accept 8-bit data characters on each clock cycle, and store the parallel data into an internal Transmit FIFO. Data is read from the Transmit FIFO and is encoded using an embedded 8B/10B encoder to improve its serial transmission characteristics. These encoded characters are then serialized and output from two Pseudo ECL (ECL referenced to +5.0V) compatible differential transmission line drivers at a bit-rate of 10 times the inp...