SLG505YC64L

SLG505YC64L Clock Synthesizer for Intel PCI-Express Chipset Features SLG505YC64 is fully compliant to Intel CK505 clock specification Ideal for both desktop and mobile application TME (Trusted Mode Enable) input to disable over-clocking support New “SR” type differential output to reduce power consumption and improve signal integrity Output Summary 2- differential CPU clock outputs @ 0.7V 1 - selectable differential CPU/SRC clock output @ 0.7V 1 - selectable differential DOT96/SRC clock output @ 0.7V 9 - differential Serial Reference Clock (SRC) clock outputs @ 0.7V 1 - differential SATA clock output @ 0.7V 1 - single-ended 48MHz clock output @ 3.3V 6 - single-ended 33MHz clock outputs @ 3.3V 1 - single-ended 14.318MHz clock output @ 3.3V CLK_REQ# inputs to support SRC clock power managewww.DataSheet4U.com ment 3.3 and low voltage (0.8V) I/O Power Supply 64 pin TSSOP Package Table 1. Frequency Select Table (FS_C, FS_B, FS_A) F S _ C 0 0 0 0 1 1 1 1 F S _ B 0 0 1 1 0 0 1 1 F S _ A 0 1 0 1 0 1 0 1 DOT_ 96 (MHz) 96.0 96.0 96.0 96.0 96.0 96.0 96.0 Pin Configuration PCI_0/CLKREQ_A# USB (MHz) 48.0 48.0 48.0 48.0 48.0 48.0 48.0 VDD_PCI PCI_1/CLKREQ_B# TME/PCI_2 PCI_3 PCI_4/SRC_5_EN PCIF_5/ITP_EN VSS_PCI VDD_48 USB/FS_A VSS_48 VDD_I/O SRC_0/DOT_96 SRC_0#/DOT_96# VSS_I/O VDD_PLL3 SRC_1/PROG_SE_1 SRC_1#/PROG_SE_2 VSS_PLL3 VDD_PLL3_I/O SRC_2/SATA SRC_2#/SATA# VSS_SRC SRC_3/CLKREQ_C# SRC_3#/CLKREQ_D# VDD_SRC_I/O SRC_4 SRC_4# VSS_SRC SRC_9 SRC_9# SRC_11#/...