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LM2650 Dataheets PDF



Part Number LM2650
Manufacturers National Semiconductor
Logo National Semiconductor
Description Synchronous Step-Down DC/DC Converter
Datasheet LM2650 DatasheetLM2650 Datasheet (PDF)

LM2650 Synchronous Step-Down DC/DC Converter June 1999 LM2650 Synchronous Step-Down DC/DC Converter General Description The LM2650 is a step-down DC/DC converter featuring high efficiency over a 3A to milliamperes load range. This feature makes the LM2650 an ideal fit in battery-powered applications that demand long battery life in both run and standby modes. The LM2650 also features a logic-controlled shutdown mode in which it draws at most 25µA from the input power supply. The LM2650 employs.

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LM2650 Synchronous Step-Down DC/DC Converter June 1999 LM2650 Synchronous Step-Down DC/DC Converter General Description The LM2650 is a step-down DC/DC converter featuring high efficiency over a 3A to milliamperes load range. This feature makes the LM2650 an ideal fit in battery-powered applications that demand long battery life in both run and standby modes. The LM2650 also features a logic-controlled shutdown mode in which it draws at most 25µA from the input power supply. The LM2650 employs a fixed-frequency pulse-width modulation (PWM) and synchronous rectification to achieve very high efficiencies. In many applications, efficiencies reach 95%+ for loads around 1A and exceed 90% for moderate to heavy loads from 0.2A to 2A. A low-power hysteretic or ″sleep″ mode keeps efficiencies high at light loads. The LM2650 enters and exits sleep mode automatically as the load crosses ″sleep in″ and ″sleep out″ thresholds. The LM2650 provides nodes for programming both thresholds via external resistors. A logic input allows the user to override the automatic sleep feature and keep the LM2650 in PWM mode regardless of the load level. An optional soft-start feature limits current surges from the input power supply at start up and provides a simple means of sequencing multiple power supplies. Features n n n n n n n n n n n n n Ultra high efficiencies (95% possible) High efficiency over a 3A to milliamperes load range Synchronous switching of internal NMOS power FETs Wide input voltage range (4.5V to 18V) Output voltage adjustable from 1.5V to 16V Automatic low-power sleep mode Logic-controlled micropower shutdown (IQSD ≤ 25 µA) Frequency adjustable up to 300 kHz Frequency synchronization with external signal Programmable soft-start Short-circuit current limiting Thermal shutdown Available in 24-lead Small-Outline package Applications n n n n n n Notebook and palmtop personal computers Portable data terminals Modems Portable Instruments Global positioning devices (GPSs) Battery-powered digital devices Typical Application LM2650-ADJ Efficiency DS012848-2 DS012848-1 Converting a Four-Cell Li Ion Battery to 5V © 1999 National Semiconductor Corporation DS012848 www.national.com Connection Diagram DS012848-14 Top View 24-Lead Small Outline Package (M) Order Number LM2650M-ADJ See Package Number M24B Pin Descriptions Pins 1, 12 2 (Refer to the Block Diagrams) Description SUB: These pins make electrical contact with the substrate of the die. Ground them. For best thermal performance, ground them to the same large, uninterrupted copper plane as the PGND pins. SLEEP LOGIC: Use this logic input to select the conversion mode; low selects PWM, high selects sleep, and high impedance (open) permits the LM2650 to move freely and automatically between the modes, using PWM for moderate to heavy loads and sleep for light loads. PGND: The ground return of the power stage. The power stage consists of the two power switches Q1 and Q2, the gate drivers DH and DL, and the linear voltage regulators VRegH and VRegL. For best electrical and thermal performance, ground these pins to a large, uninterrupted copper plane. SW: The output node of the power stage. It swings from slightly below ground to slightly below the voltage to PVIN. To minimize the effects of switching noise on nearby circuitry, keep all traces originating from SW short and to the point. Route all traces carrying signals well away from the SW traces. PVIN: The positive supply rail of the power stage. Bypass each PVIN pin to PGND with a 0.1 µF capacitor. Use capacitors having low ESL and low ESR, and locate them close to the IC. BOOT: The positive supply rail of the high-side gate driver DH. Connect a 0.1 µF capacitor from this node to SW. Bootstrapping action creates a supply rail about 9V above that at PVIN, and DH uses this rail to override the gate of the NMOS power FET Q1. Overriding ensures low RDS(on). FB: The feedback input. VDD: An internal regulator steps the input voltage down to a 4V rail used by the signal-level circuitry. VDD is the output node of this regulator. Bypass VDD to GND close to the IC with a 0.2 µF capacitor. COMP: The inverting input of the error amplifier EA. EA OUT: The output node of the error amplifier EA. SS: The soft start node. Connect a capacitor from SS to GND. GND: The ground return of the signal-level circuitry. VIN: The positive supply rail of the internal 4V regulator. Bypass VIN to GND close to the IC with a 0.1 µF capacitor. FREQ ADJ: The LM2650 switches at a nominal 90 kHz. Connect a resistor between FREQ ADJ and GND to adjust the frequency up from the nominal. Use the graph under Typical performance Characteristics to select the resistor. SYNC: The synchronization input. If the switching frequency is to be synchronized with an external clock signal, apply the clock signal here. SD: Use this logic input to control shutdown; pull low for operation, high for shutdown. SLEEP OUT ADJ (SOA): The value of the resistor connected .


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