PRELIMINARY
CY7C1410V18 CY7C1425V18 CY7C1412V18 CY7C1414V18
36-Mbit QDR-II™ SRAM 2-Word Burst Architecture
Features
Separate Independent Read and Write data ports — Supports concurrent transactions 200-MHz clock for high bandwidth 2-Word Burst on all accesses Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 400 MH...
