Document
iT4021D 20 Gb/s (12.5 Gb/s RZ) T-Type Flip-Flop
(Advanced Information)
Description
The iT4021D is a high-speed T-type flip-flop fabricated using 1µm HBT GaAs technology. The T flip-flop consists of a master-slave latch, closed-in feedback, and is designed using an ECL topology in order to guarantee high-speed operation. The data input may be either AC or DC coupled, the output is DC coupled. At the input side the internal 50-ohm resistors avoid the need for external terminations for impedance matching. The iT4021D uses SCFL I/O levels and is designed to allow for either single-ended or differential data input/output. An on-chip, output buffer produces an excellent eye diagram up to an output rate of 12.5 Gb/s rate (20 Gb/s NRZ or 12.5 Gb/s RZ input data rate) or 14 GHz input clock. The high output voltage, excellent rise and fall times, and the high-quality eye diagram at all clock frequencies makes the iT4021D suitable for very-high-speed, complex digital applications such as differential encoding, clock dividers, and edge detectors.
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Features
Data rate range: 20 NRZ (12.5 RZ) Gb/s Maximum clock frequency as clock divider: 14 GHz 900 mVpp typical single-ended output Input sensitivity: Single ended input >250 mV Jitter transfer RMS: <1 ps Output rise time (20% - 80%): <27 ps Output fall time (20% - 80%): <24 ps DC or AC coupled data input 50-ohm matched DC-coupled data output Differential or single-ended inputs and outputs Full SCFL I/O level compatibility Low power consumption: 0.71 W
Device Diagram
Timing Diagram
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This is an Advanced data sheet. See “Product Status Definitions” on Web site or catalog for product development status. April 24, 2007 Doc. 4049 Rev 1.0 1
iTerra Communications 2400 Geng Road, Ste. 100, Palo Alto, CA 94303 Phone (650) 424-1937, Fax (650) 424-1938
iT4021D 20 Gb/s (12.5 Gb/s RZ) T-Type Flip-Flop
(Advanced Information)
Absolute Maximum Ratings
Stresses in excess of those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only. Functional operation of www.DataSheet4U.com the device at these or any other conditions above those indicated in the operational section of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Symbol Vee VDH VDL Ta Tstg
Parameters/conditions Power supply voltage Data/clock input voltage level, high level Data/clock input voltage level, low level Operating temperature range – die Storage temperature
Min. -5.5 -1.2 -1.2 -15 -65
Max 0 1.2 1.2 125 150
Units V V V °C °C
Recommended Operational Conditions
Symbol Ta Vee VDH VDL Vindc Vipp
Parameters/conditions Operating temperature range – die Power supply voltage Data/clock input voltage level, high level (single ended) Data/clock input voltage level, low level (single ended) DC input voltage (with DC-coupled input) Data/clock input voltage level (single-Ended peak to peak)
Min. 0
Typ
Max 85
Units °C V
-5.2
-0.1 -0.6 -0.3
0.25 -0.25 0 0.5
V V V V
Electrical Characteristics
1. Electrical characteristics at ambient temperature. 2. In case of single-ended inputs, the unused ones must be tied to Vindc which must be set close to the mean value of the used one. 3. Output change state on input rising edge. 4. Duty cycle 50%. Asymmetrical duty cycle may reduce maximum toggling frequency. 25 Gb/s input working data rate is possible tolerating additional jitter degradations.
Symbol Vee VDH VDL Vindiffpp Vindc VQH VQL Tr Tf Tdl FMAx
Parameters Power supply voltage Data/clock input voltage level, high level (single ended) Data/clock input voltage level, low level (single ended) Data/clock input voltage level differential peak to peak DC input voltage (with DC-coupled input) (2)
Min -5.45 -0.5 -1 0.50 -0.75 -0.05 -0.95
Typ -5.2 0.25 -0.25 1.0 0 0 -0.9 27 24
Max -4.85 0.5 0 1.8 0.25 0 -0.85
Units V V V
V V V ps ps
Data output voltage amplidude high Data output voltage amplidude low Output rise time (20% - 80%) Output fall time (20% - 80%) Input to data output delay
(3) (4)
125 0
135 12.5
145 14
ps GHz
Clock frequency As a clock divider
www.iterrac.com
This is an Advanced data sheet. See “Product Status Definitions” on Web site or catalog for product development status. April 24, 2007 Doc. 4049 Rev 1.0 2
iTerra Communications 2400 Geng Road, Ste. 100, Palo Alto, CA 94303 Phone (650) 424-1937, Fax (650) 424-1938
iT4021D 20 Gb/s (12.5 Gb/s RZ) T-Type Flip-Flop
(Advanced Information)
Electrical Characteristics
(cont.)
Symbol RMAx RLin RLout
Parameters Input data rate(4) Minimum input return loss (up to 15 GHz) Minimum output return loss (up to 15 GHz) Minimum pulse width Peak to peak jitter RMS jitter Power supply current Power dissipation
Min 0
Typ 12.5 20 5.5 40
Max 20 (-25)
Units Gb/s dB dB ps
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MPW Jpp Jrms Ic Pd
7
8 1.3 136 0.71
9
ps ps mA W
Eye Diagram Performance
Die measurement Vee: -5.2 V NR.