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DS1286 Dataheets PDF



Part Number DS1286
Manufacturers Dallas Semiconductor
Logo Dallas Semiconductor
Description (DS1284 / DS1286) Watchdog Timekeepers
Datasheet DS1286 DatasheetDS1286 Datasheet (PDF)

DS1284/DS1286 Watchdog Timekeepers www.maxim-ic.com GENERAL DESCRIPTION The DS1284/DS1286 watchdog timekeepers are self-contained real-time clocks, alarms, watchdog timers, and interval timers in a 28-pin JEDEC DIP and encapsulated DIP package. The DS1286 contains an embedded lithium energy source and a www.DataSheet4U.com quartz crystal, which eliminates the need for any external circuitry. The DS1284 requires an external quartz crystal and a VBAT source, which could be a lithium battery. Data.

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DS1284/DS1286 Watchdog Timekeepers www.maxim-ic.com GENERAL DESCRIPTION The DS1284/DS1286 watchdog timekeepers are self-contained real-time clocks, alarms, watchdog timers, and interval timers in a 28-pin JEDEC DIP and encapsulated DIP package. The DS1286 contains an embedded lithium energy source and a www.DataSheet4U.com quartz crystal, which eliminates the need for any external circuitry. The DS1284 requires an external quartz crystal and a VBAT source, which could be a lithium battery. Data contained within 64 8-bit registers can be read or written in the same manner as byte-wide static RAM. Data is maintained in the watchdog timekeeper by intelligent control circuitry that detects the status of VCC and write protects memory when VCC is out of tolerance. The lithium energy source can maintain data and real time for over 10 years in the absence of VCC. Watchdog timekeeper information includes hundredths of seconds, seconds, minutes, hours, day, date, month, and year. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap year. The DS1284/DS1286 operate in either 24-hour or 12hour format with an AM/PM indicator. The devices provide alarm windows and interval timing between 0.01 seconds and 99.99 seconds. The real-time alarm provides for preset times of up to one week. FEATURES Keeps Track of Hundredths of Seconds, Seconds, Minutes, Hours, Days, Date of the Month, Months, and Years; Valid Leap Year Compensation Up to 2100 Watchdog Timer Restarts an Out-of-Control Processor Alarm Function Schedules Real-Time-Related Activities Embedded Lithium Energy Cell Maintains Time, Watchdog, User RAM, and Alarm Information Programmable Interrupts and Square-Wave Outputs Maintain JEDEC Footprint All Registers are Individually Addressable via the Address and Data Bus Accuracy is Better than ±1 Minute/Month at +25°C (EDIP) Greater than 10 Years of Timekeeping in the Absence of VCC 50 Bytes of User NV RAM Underwriters Laboratory (UL) Recognized -40°C to +85°C Industrial Temperature Range Option Pin Configurations appear at end of data sheet. ORDERING INFORMATION PART TEMP RANGE 0°C to +70°C DS1284 -40°C to +85°C DS1284N 0°C to +70°C DS1284Q 0°C to +70°C DS1284Q+ 0°C to +70°C DS1284Q/T&R 0°C to +70°C DS1284Q+T&R -40°C to +85°C DS1284QN -40°C to +85°C DS1284QN+ -40°C to +85°C DS1284QN/T&R -40°C to +85°C DS1284QN+T&R 0°C to +70°C DS1286 -40°C to +85°C DS1286I -40°C to +85°C DS1286I+ + Denotes a lead-free/RoHS-compliant package. VOLTAGE (V) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 PIN-PACKAGE 28 DIP (600 mils) 28 DIP (600 mils) 28 PLCC 28 PLCC 28 PLCC/Tape and Reel 28 PLCC/Tape and Reel 28 PLCC 28 PLCC 28 PLCC/Tape and Reel 28 PLCC/Tape and Reel 28 EDIP (720 mils) 28 EDIP (720 mils) 28 EDIP (720 mils) TOP MARK* DS1284 DS1284 N DS1284Q DS1284Q DS1284Q DS1284Q DS1284QN DS1284QN DS1284QN DS1284QN DS1286 DS1286 IND DS1286 IND * A “+” anywhere on the top mark indicates a lead-free package. 1 of 18 REV: 032406 DS1284/DS1286 OPERATION—READ REGISTERS The DS1284/DS1286 execute a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable) and OE (output enable) are active (low). The unique address specified by the six address inputs (A0–A5) defines which of the 64 registers is to be accessed. Valid data is available to the eight data output drivers within tACC (access time) after the last address input signal is stable, provided that CE and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the latter occurring signal (CE or OE) and the limiting parameter is either tCO for CE or tOE for OE rather than address access. OPERATION—WRITE REGISTERS The DS1284/DS1286 are in the write mode whenever the WE and CE signals are in the active-low state after the address inputs are stable. The latter occurring falling edge of CE or WE determines the start of www.DataSheet4U.com the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery state (tWR) before another cycle can be initiated. Data must be valid on the data bus with sufficient data setup (tDS) and data hold time (tDH) with respect to the earlier rising edge of CE or WE. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active), then WE will disable the outputs in tODW from its falling edge. DATA RETENTION The watchdog timekeeper provides full functional capability when VCC is greater than VTP. Data is maintained in the absence of VCC without any additional support circuitry. The DS1284/DS1286 constantly monitor VCC. Should the supply voltage decay, the watchdog timekeeper automatically write protects itself, and all inputs to the registers become “don’t care.” Both IN.


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