Document
Si 5 33
REVISION D
D U A L F R E Q U E N C Y C R Y S TA L O S C I L L A T O R (XO ) (10 M H Z T O 1.4 G H Z )
Features
Available with any-rate output frequencies from 10 MHz to 945 MHz and select frequencies to 1.4 GHz 2 selectable output frequencies 3rd generation DSPLL® with superior jitter performance 3x better frequency stability than www.DataSheet4U.com SAW-based oscillators Pin 1 output enable (OE) Internal fixed crystal frequency ensures high reliability and low aging Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout Pb-free/RoHS-compliant
Si5602
Applications
SONET/SDH Networking SD/HD video Clock and data recovery FPGA/ASIC clock generation
Ordering Information: See page 7.
Description
The Si533 dual frequency XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low jitter clock at high frequencies. The Si533 is available with any-rate output frequency from 10 to 945 MHz and select frequencies to 1400 MHz. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si533 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si533 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators.
Pin Assignments: See page 6. (Top View)
OE FS GND
1 2 3
6 5 4
VDD
CLK– CLK+
LVDS/LVPECL/CML
Functional Block Diagram
V DD CLK– CLK+
OE FS
1 2 3
CMOS
6 5 4
VDD
NC CLK+
Fixed Frequency XO
Any-rate 10–1400 MHz DSPLL® Clock Synthesis
GND
OE
FS
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si533
Si5 33
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Supply Voltage1 Symbol VDD Test Condition 3.3 V option 2.5 V option 1.8 V option Supply Current
www.DataSheet4U.com
Min 2.97 2.25 1.71 — — — — — 0.75 x VDD — –40
Typ 3.3 2.5 1.8 111 99 90 81 60 — — —
Max 3.63 2.75 1.89 121 108 98 88 75 — 0.5 85
Units
V
IDD
Output enabled LVPECL CML LVDS CMOS Tristate mode
mA
Output Enable (OE) and Frequency Select (FS)2 Operating Temperature Range TA
VIH VIL
V ºC
Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details. 2. OE and FS pins include a 17 kΩ pullup resistor to VDD.
Table 2. CLK± Output Frequency Characteristics
Parameter
Nominal Frequency1,2
Symbol fO
Test Condition LVPECL/LVDS/CML CMOS
Min
10 10 — –7 –20 –50
Typ
— — ±1.5 — — — — —
Max
945 160 — +7 +20 +50 ±3 ±10
Units
MHz
Initial Accuracy
fi
Measured at +25 °C at time of shipping
ppm
Temperature Stability1,3 Frequency drift over first year Frequency drift over 15 year life
ppm ppm ppm
Aging
fa
— —
Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO.
2
Rev. 1.1
Si533
Table 2. CLK± Output Frequency Characteristics (Continued)
Parameter Symbol Test Condition
Temp stability = ±7 ppm Total Stability Temp stability = ±20 ppm Temp stability = ±50 ppm Powerup Time4 Settling Time After FS Change
www.DataSheet4U.com
Min
— — — — —
Typ
— — — — —
Max
±20 ±31.5 ±61.5 10 10
Units
ppm ppm ppm ms ms
tOSC tFRQ
Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO.
Table 3. CLK± Output Levels and Symmetry
Parameter LVPECL Output Option1 Symbol VO
VOD VSE
Test Condition
mid-level swing (diff) swing (single-ended) mid-level swing (diff)
Min
VDD – 1.42 1.1 0.55 1.125 0.5
Typ
—
Max
VDD – 1.25 1.9 0.95 1.275 0.9
Units
V VPP VPP V VPP
— —
1.20 0.7
LVDS Output Option2
VO
VOD
CML Output Option2
VO VOD
mid-level swing (diff) IOH = 32 mA
IOL = 32 mA
— 0.70
0.8 x VDD
VDD – 0.75 0.95 — — — 1 —
— 1.20
VDD
V
VPP V
CMOS Output Option3
VOH VOL
— — — 45
0.4 350 — 55
Rise/Fall time (20/80%)
tR, tF
LVPECL/LVDS/CML CMOS with CL = 15 pF
ps ns %
Symmetry (duty cycle)
SYM
LVPECL: LVDS: CMOS:
VDD – 1.3 V (diff) 1.25 V (diff) VDD/2
Notes: 1. 50 Ω to VDD – 2.0 V. 2. Rterm = 100 Ω (differential). 3. CL = 15 pF
Rev. 1.1
3
Si5 33
Table 4. CLK± Output Phase Jitter
Param.