46V16M8

PRELIMINARY‡ 128Mb: x4, x8, x16 DDR SDRAM DOUBLE DATA RATE (DDR) SDRAM FEATURES VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data www.DataSheet4U.com capture (x16 has two – one per byte) Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Differential clock inputs (CK and CK#) Commands entered on each positive CK edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Data mask (DM) for masking write data (x16 has two – one per byte) x16 has programmable IOL/IOH option Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes Longer lead TSOP for improved reliability (OCPL) 2.5V I/O (SSTL_2 compatible) MT46V32M4 – 8 Meg x 4 x 4 banks MT46V16M8 – 4 Meg x 8 x 4 banks MT46V8M16 – 2 Meg x 16 x 4 banks For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/datasheets PIN ASSIGNMENT (TOP VIEW) 66-Pin TSOP x4 x8 x16 VDD VDD VDD NC DQ0 DQ0 VDDQ VDDQ VDDQ NC DQ1 NC DQ0 DQ1 DQ2 VSSQ VSSQ VssQ NC DQ3 NC NC DQ2 DQ4 VDDQ VDDQ VDDQ NC DQ5 NC DQ1 DQ3 DQ6 VSSQ VSSQ VssQ NC DQ7 NC NC NC NC VDDQ VDDQ VDDQ NC NC LDQS NC NC NC VDD VDD VDD NC DNU DNU NC NC LDM WE# WE# WE# CAS# CAS# CAS# RAS# RAS# RAS# CS# CS# CS# NC NC NC BA0 BA0 BA0 BA1 BA1 BA1 A10/AP A10/AP A10...