SSTVF16859

SSTVF16859 13-bit 1 : 2 SSTL_2 registered buffer for DDR Rev. 02 — 19 July 2005 Product data sheet 1. General description The SSTVF16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V for PC1600-PC2700 applications or between 2.5 V and 2.7 V for PC3200 applications. All inputs are compatible with the JEDEC standard for SSTL_2 with Vref normally at 0.5 × VDD, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible, which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTVF16859 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM and SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The device data inputs consist of different receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential (CK and CK) to be compatible with DRAM devices that are installed on the DIMM. Data are registered at the crossing of CK going HIGH, and CK going LOW. However, since the control inputs to the SDRAM change at only half the d...