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EDE5108AGBG Dataheets PDF



Part Number EDE5108AGBG
Manufacturers Elpida Memory
Logo Elpida Memory
Description 512M bits DDR2 SDRAM
Datasheet EDE5108AGBG DatasheetEDE5108AGBG Datasheet (PDF)

DATA SHEET 512M bits DDR2 SDRAM EDE5108AGBG (64M words × 8 bits) Specifications • Density: 512M bits • Organization ⎯ 16M words × 8 bits × 4 banks • Package: 60-ball FBGA www.DataSheet4U.com ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Data rate: 667Mbps/533Mbps (max.) • 1KB page size ⎯ Row address: A0 to A13 ⎯ Column address: A0 to A9 • Four internal banks for concurrent operation • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • Burst type (BT): ⎯ Sequential (4, 8) ⎯.

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DATA SHEET 512M bits DDR2 SDRAM EDE5108AGBG (64M words × 8 bits) Specifications • Density: 512M bits • Organization ⎯ 16M words × 8 bits × 4 banks • Package: 60-ball FBGA www.DataSheet4U.com ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Data rate: 667Mbps/533Mbps (max.) • 1KB page size ⎯ Row address: A0 to A13 ⎯ Column address: A0 to A9 • Four internal banks for concurrent operation • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • Burst type (BT): ⎯ Sequential (4, 8) ⎯ Interleave (4, 8) • /CAS Latency (CL): 3, 4, 5 • Precharge: auto precharge option for each burst access • Driver strength: normal/weak • Refresh: auto-refresh, self-refresh Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted /CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality • Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4 organization • /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation • Refresh cycles: 8192 cycles/64ms ⎯ Average refresh period 7.8μs at 0°C ≤ TC ≤ +85°C 3.9μs at +85°C < TC ≤ +95°C • Operating case temperature range ⎯ TC = 0°C to +95°C Document No. E0917E30 (Ver. 3.0) Date Published September 2006 (K) Japan Printed in Japan URL: http://www.elpida.com ©Elpida Memory, Inc. 2006 EDE5108AGBG Ordering Information Part number EDE5108AGBG-6E-E EDE5108AGBG-5C-E Mask version G Organization (words × bits) 64M × 8 Internal Banks 4 Speed bin (CL-tRCD-tRP) DDR2-667 (5-5-5) DDR2-533 (4-4-4) Package 60-ball FBGA Part Number E D E 51 08 A G BG - 6E - E Elpida Memory www.DataSheet4U.com Type D: Monolithic Device Product Family E: DDR2 Density / Bank 51: 512Mb /4-bank Organization 08: x8 Environment code E: Lead Free (RoHS compliant) Speed 6E: DDR2-667 (5-5-5) 5C: DDR2-533 (4-4-4) Package BG: FBGA Die Rev. Power Supply, Interface A: 1.8V, SSTL_18 Data Sheet E0917E30 (Ver. 3.0) 2 EDE5108AGBG Pin Configurations /xxx indicates active low signal. 60-ball FBGA 1 A VDD NU/ /RDQS VSS B DQ6 VSSQ DM/RDQS C VDDQ D www.DataSheet4U.com 2 3 7 8 9 VSSQ /DQS VDDQ DQS VDDQ DQ2 VSSDL /RAS /CAS A2 A6 A11 NC (Top view) VSSQ DQ0 VSSQ CK /CK /CS A0 A4 A8 A13 VSS VDD DQ7 VDDQ DQ5 VDD ODT DQ1 VDDQ VSSQ DQ3 VSS /WE BA1 A1 A5 A9 NC DQ4 E VDDL VREF F CKE G NC H A10 J VSS K L VDD A12 A3 A7 BA0 Pin name A0 to A13 BA0, BA1 DQ0 to DQ7 DQS, /DQS RDQS, /RDQS /CS /RAS, /CAS, /WE CKE CK, /CK DM Function Address inputs Bank select Data input/output Differential data strobe Differential data strobe for read Chip select Command input Clock enable Differential clock input Write data mask Pin name ODT VDD VSS VDDQ VSSQ VREF VDDL VSSDL NC* NU* 1 2 Function ODT control Supply voltage for internal circuit Ground for internal circuit Supply voltage for DQ circuit Ground for DQ circuit Input reference voltage Supply voltage for DLL circuit Ground for DLL circuit No connection Not usable Notes: 1. Not internally connected with die. 2. Don’t use other than reserved functions. Data Sheet E0917E30 (Ver. 3.0) 3 EDE5108AGBG CONTENTS Specifications.................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Pin Configurations .........................................................................................................................................3 Electrical Specifications.................................................................................................................................5 Block Diagram .............................................................................................................................................23 Pin Function.................................................................................................................................................24 Command Operation ...................................


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