ASM5I9658

July 2005 rev 0.2 3.3V 1:10 LVCMOS PLL Clock Generator Features ƒ ƒ ƒ 1:10 PLL based low-voltage clock generator Supports zero-delay operation 3.3V power supply ASM5I9658 and the reference clock frequency determines the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the ASM5I9658 is running at either 2x or 4x of the reference clock frequency. The ASM5I9658 has a differential LVPECL reference input along with an external feedback input. The ASM5I9658 is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The ASM5I9658 is fully 3.3V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVCMOS except signals while the outputs prov...