S5933QE

www.DataSheet4U.com PCI Interface Device Summary S5933QE Revision 4 January 6, 1999 Factory Device Update The following are all known device and document errors for the AMCC S5933 PCI Matchmaker revision QE and the 1998 device data book. The workarounds described below are factory suggestions and are not to imply the only or all possible solutions. Contact your local Field Application Engineer for new workaround developements. Also contact your AMCC FAE or local Insight Technical Sales Engineer for the latest design notes and data book corrections or see the AMCC home page at www.amcc.com. D8: Bus Master Burst Write Operation with an Asynchronous FIFO Interface Description: When performing a bus master write to the PCI bus, if only one location of the FIFO remains full, the S5933 deasserts FRAME# on the next clock to indicate the last data phase is in progress. If another value is written from the add-on at the right moment, an internal condition may cause IRDY# to remain asserted to sustain the burst, but FRAME# has already been deasserted. Workaround: Externally synchronizing WRFIFO# or WR# to BPCLK moves the rising edge of the write strobe to prevent this event from occurring. Request separate D8 applications note from your local FAE or Insight TSE for more detail. Status: No factory plan to re-spin. D14.1: False Add-On to PCI FIFO Empty Indication Description: If the last data in the Add-On to PCI FIFO is written by the S5933 to the PCI bus and receives a target retry...