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BUK95/96/9E06-55B
N-channel TrenchMOS™ logic level FET
Rev. 03 — 30 November 2004 Product data sheet
1. Product profile
1.1 General description
N-channel enhancement mode field-effect power transistor in a plastic package using Philips High-Performance Automotive (HPA) TrenchMOS™ technology, featuring very low on-state resistance.
1.2 Features
s TrenchMOS™ technology s 175 °C rated s Q101 compliant s Logic level compatible.
1.3 Applications
s Automotive systems s Motors, lamps and solenoids s 12 V and 24 V loads s General purpose power switching.
1.4 Quick reference data
s EDS(AL)S ≤ 679 mJ s ID ≤ 75 A s RDSon = 5.1 mΩ (typ) s Ptot ≤ 258 W.
2. Pinning information
Table 1: Pin 1 2 3 mb Pinning Description gate (G) drain (D) source (S) mounting base; connected to drain (D)
123
3
[1]
Simplified outline
mb mb
Symbol
mb
D
G
mbb076
S
2 1 1 2 3
SOT226 (I2-PAK)
SOT404 (D2-PAK)
SOT78 (TO-220AB)
[1] It is not possible to make a connection to pin 2 of the SOT404 package.
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Philips Semiconductors
BUK95/96/9E06-55B
N-channel TrenchMOS™ logic level FET
3. Ordering information
Table 2: Ordering information Package Name BUK9506-55B BUK9606-55B BUK9E06-55B TO-220AB D2-PAK I2-PAK Description Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB Version SOT78 Type number
Plastic single-ended surface mounted package (Philips version of D2-PAK); SOT404 3 leads (one lead cropped) Plastic single-ended package (Philips version of I2-PAK); low-profile 3 lead TO-220AB SOT226
4. Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) Tmb = 25 °C; VGS = 5 V; Figure 2 and 3 Tmb = 100 °C; VGS = 5 V; Figure 2 IDM Ptot Tstg Tj IDR IDRM peak drain current total power dissipation storage temperature junction temperature reverse drain current (DC) peak reverse drain current Tmb = 25 °C Tmb = 25 °C; pulsed; tp ≤ 10 µs unclamped inductive load; ID = 75 A; VDS ≤ 55 V; RGS = 50 Ω; VGS = 5 V; starting at Tj = 25 °C
[1] [2] [1] [2] [2]
Conditions RGS = 20 kΩ
Min −55 −55 -
Max 55 55 ±15 146 75 75 587 258 +175 +175 146 75 587 679
Unit V V V A A A A W °C °C A A A mJ
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tmb = 25 °C; Figure 1
Source-drain diode
Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy
[1] [2]
Current is limited by power dissipation chip rating Continuous current is limited by package
9397 750 13519
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 30 November 2004
2 of 15
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Philips Semiconductors
BUK95/96/9E06-55B
N-channel TrenchMOS™ logic level FET
120 Pder (%) 80
03aa16
150 ID (A) 100
03nh85
Capped at 75 A due to package 40 50
0 0 50 100 150 Tmb (°C) 200
0 0 50 100 150 Tmb ( °C) 200
P tot P der = ---------------------- × 100 % P °
tot ( 25 C )
VGS ≥ 5 V
Fig 1. Normalized total power dissipation as a function of mounting base temperature.
103 ID (A) 102 Limit RDSon = VDS / ID
Fig 2. Continuous drain current as a function of mounting base temperature.
03nh83
tp = 10 µ s
100 µ s Capped at 75 A due to package DC 1 ms 10 ms 100 ms
10
1 10-1
1
10
VDS (V)
102
Tmb = 25 °C; IDM is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 13519
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 30 November 2004
3 of 15
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Philips Semiconductors
BUK95/96/9E06-55B
N-channel TrenchMOS™ logic level FET
5. Thermal characteristics
Table 4: Rth(j-mb) Rth(j-a) Thermal characteristics Conditions Min Typ 60 50 Max 0.58 Unit K/W K/W K/W thermal resistance from junction to mounting base Figure 4 thermal resistance from junction to ambient SOT78 (TO-220AB) and SOT226 (I2-PAK) SOT404 (D2-PAK) vertical in free air mounted on a printed-circuit board; minimum footprint; vertical in still air Symbol Parameter
5.1 Transient thermal impedance
03nh84
1 Zth(j-mb) (K/W) 10
-1
δ = 0.5
0.2 0.1 0.05 0.02
10-2
P δ= tp T
single shot
10-3 10-6 10-5 10-4 10-3 10-2 10-1
tp T
t
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 13519
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 30 November 2004
4 of 15
www.DataSheet4U.com
Philips Semiconductors
BUK95/96/9E06-55B
N-channel TrenchMOS™ logic level FET
6. Characteristics
Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol V(BR)DSS Parameter drain-source breakdown voltage Conditions ID = 250 µA; VGS = 0 V Tj = 25 °C Tj = −55 °C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 and 10 Tj = 25 °C Tj = 175 °C Tj = −55 °C IDSS drain-source leakage curren.