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NT5SV32M8BS Dataheets PDF



Part Number NT5SV32M8BS
Manufacturers Nanya Technology
Logo Nanya Technology
Description (NT5SVxxMxxBx) 256Mb SDRAM
Datasheet NT5SV32M8BS DatasheetNT5SV32M8BS Datasheet (PDF)

www.DataSheet4U.com NT5SV64M4BS / NT5SV64M4BT NT5SV32M8BS / NT5SV32M8BT NT5SV16M16BS / NT5SV16M16BT 256Mb Synchronous DRAM Features • High Performance: 6K 75B Units CL=3 CL=3 fCK tCK tAC tAC Clock Frequency Clock Cycle Clock Access Time1 Clock Access Time2 166 6 — 5 133 MHz 7.5 — 5.4 ns ns ns 1. Terminated load. See AC Characteristics on page 37 2. Unterminated load. See AC Characteristics on page 37 3. tRP = tRCD = 2 CKs • Single Pulsed RAS Interface • Fully Synchronous to Positive Clock Ed.

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www.DataSheet4U.com NT5SV64M4BS / NT5SV64M4BT NT5SV32M8BS / NT5SV32M8BT NT5SV16M16BS / NT5SV16M16BT 256Mb Synchronous DRAM Features • High Performance: 6K 75B Units CL=3 CL=3 fCK tCK tAC tAC Clock Frequency Clock Cycle Clock Access Time1 Clock Access Time2 166 6 — 5 133 MHz 7.5 — 5.4 ns ns ns 1. Terminated load. See AC Characteristics on page 37 2. Unterminated load. See AC Characteristics on page 37 3. tRP = tRCD = 2 CKs • Single Pulsed RAS Interface • Fully Synchronous to Positive Clock Edge • Four Banks controlled by BA0/BA1 (Bank Select) • • • • • • • • • • • • • • • • Programmable CAS Latency: 2, 3 Programmable Burst Length: 1, 2, 4, 8 Programmable Wrap: Sequential or Interleave Multiple Burst Read with Single Write Option Automatic and Controlled Precharge Command Data Mask for Read/Write control (x4, x8) Dual Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode Standard Power operation 8192 refresh cycles/64ms Random Column Address every CK (1-N Rule) Single 3.3V ± 0.3V Power Supply LVTTL compatible Package: 54-pin 400 mil TSOP-Type II Lead-free & Halogen-free product available Description The NT5SV64M4BS, NT5SV64M4BT, NT5SV32M8BS, NT5SV32M8BT, NT5SV16M16BS, and NT5SV16M16BT are four-bank Synchronous DRAMs organized as 16Mbit x 4 I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4 Bank, respectively. These synchronous devices achieve high-speed data transfer rates of up to 166MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. RAS, CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock (CK). Internal chip operating modes are defined by combinations of these signals and a command decoder initiates the necessary timings for each operation. A fifteen bit address bus accepts address data in the conventional RAS/CAS multiplexing style. Thirteen row addresses (A0-A12) and two bank select addresses (BA0, BA1) are strobed with RAS. Eleven column addresses (A0-A9, A11) plus bank select addresses and A10 are strobed with CAS. Column address A11 is dropped on the x8 device, and column addresses A11 and A9 are dropped on the x16 device. Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A12, BA0, BA1 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166MHz is possible depending on burst length, CAS latency, and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. REV 1.4 Oct 2006 1 © NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. www.DataSheet4U.com NT5SV64M4BS / NT5SV64M4BT NT5SV32M8BS / NT5SV32M8BT NT5SV16M16BS / NT5SV16M16BT 256Mb Synchronous DRAM Ordering Information Speed Grade Organization 64M x 4 32M x 8 16M x 16 64M x 4 32M x 8 16M x 16 64M x 4 32M x 8 16M x 16 64M x 4 32M x 8 16M x 16 Part Number NT5SV64M4BS-6K NT5SV32M8BS-6K NT5SV16M16BS-6K NT5SV64M4BT-6K NT5SV32M8BT-6K NT5SV16M16BT-6K NT5SV64M4BS-75B NT5SV32M8BS-75B NT5SV16M16BS-75B NT5SV64M4BT-75B NT5SV32M8BT-75B NT5SV16M16BT-75B Clock Frequency CL-tRCD-tRP 166MHz-3-3-3 166MHz-3-3-3 166MHz-3-3-3 166MHz-3-3-3 166MHz-3-3-3 166MHz-3-3-3 133MHz-3-3-3 133MHz-3-3-3 133MHz-3-3-3 133MHz-3-3-3 133MHz-3-3-3 133MHz-3-3-3 Note PC166 PC166 PC166 PC166 PC166 PC166 PC133 PC133 PC133 PC133 PC133 PC133 Package Power 400mil 54-PIN TSOP II Lead-Free 400mil 54-PIN TSOP II 400mil 54-PIN TSOP II Lead-Free 400mil 54-PIN TSOP II 3.3V 3.3V 3.3V 3.3V CL = CAS Latency Lead-free products are also halogen-free Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.nanya.com REV 1.4 Oct 2006 2 © NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. www.DataSheet4U.com NT5SV64M4BS / NT5SV64M4BT NT5SV32M8BS / NT5SV32M8BT NT5SV16M16BS / NT5SV16M16BT 256Mb Synchronous DRAM Pin Assignments for Planar Components (Top View) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ.


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