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Freescale Semiconductor Technical Data
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MC33780 Rev 3.0, 5/2006
Dual DBUS Master with Differential Drive and Frequency Spreading
The 33780 is a master device for two differential DBUS buses. It contains the logic to interface the buses to a standard serial peripheral interface (SPI) port and the analog circuitry to drive data and power over the bus as well as receive data from the remote slave devices. The differential mode of the 33780 generates lower electromagnetic interference (EMI) in situations where data rates and wiring make this a problem. Frequency spreading further reduces interference by spreading the energy across many channels, reducing the energy in any single channel. Features • Two Independent DBUS I/Os • Common SPI Interface for All Operations • Open-Drain Interrupt Output with Pull-up • Maskable Interrupts for Send and Receive Data Status • Automatic Message Cyclical Redundancy Checking (CRC) Generation and Checking • Four-Stage Transmit and Receive Buffers • 8- to 16-Bit Messages with 0- to 8-Bit CRC • Independent Frequency Spreading for Each Channel • Pb-Free Packaging Designated by Suffix Code EG
33780
DIFFERENTIAL DBUS MASTER
EG (Pb-FREE SUFFIX) 98ASB42567B 16-TERMINAL SOICW
ORDERING INFORMATION
Device MC33780EG/R2 Temperature Range (TA) -40°C to 85°C Package 16 SOICW
+5.0 V
+25 V
MCU VCC SCLK CS MOSI MISO RST INT CLK GND VCC
33780 VSUP Twisted Pair SCLK CS MOSI MISO RST INT CLK GND D0H D0L D1H D1L DSI/DBUS SLAVE 33793
DSI/DBUS SLAVE 33793
4.7 nF capacitors from D0H, D0L, D1H and D1L to circuit ground are required for proper operation.
Figure 1. 33780 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
www.DataSheet4U.com INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VCC
VSUP
CLK DSIF DSIS Protocol Engine DSIR DSIF DSIS DSIR SCLK MISO MOSI CS INT RST
DBUS Driver/Receiver
D0H D0L
Spreader
DBUS Driver/Receiver
D1H D1L
SPI, Registers and Interrupt Generator
TLIM
GND GND GND
Figure 2. 33780 Internal Block Diagram
33780
2
Analog Integrated Circuit Device Data Freescale Semiconductor
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TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
RST CS INT MOSI SCLK MISO CLK GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
GND D0L D0H VSUP D1H D1L GND VCC
Figure 3. 33780 Terminal Connections Table 1. 33780 Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Descriptions section beginning on page 13.
Terminal 1 2 Terminal Name RST CS Terminal Function Reset Input Formal Name IC Reset SPI Chip Select Input Definition A low level on this terminal returns all registers to a known state as indicated in the section entitled Register and Bit Descriptions. When this signal is high, SPI signals are ignored. Asserting this terminal low star.