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16Mx64bits PC100 SDRAM Unbuffered DIMM
based on 16Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM71V16655BT8 Series
DESCRIPTION Preliminary
The Hynix HYM71V16655BT8 Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of eight 16Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB. The Hynix HYM71V16655BT8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes memory. The Hynix HYM71V16655BT8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
FEATURES
• • • • PC100MHz support 168pin SDRAM Unbuffered DIMM Serial Presence Detect with EEPROM 1.15” (29.21mm) Height PCB with single sided components Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface - 1, 2, 4 or 8 for Interleave Burst • Data mask function by DQM • Programmable CAS Latency ; 2, 3 Clocks • • • • • SDRAM internal banks : four banks Module bank : one physical bank Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4 or 8 or Full page for Sequential Burst •
•
ORDERING INFORMATION
Part No.
HYM71V16655BT8-8 HYM71V16655BT8-P HYM71V16655BT8-S
Clock Frequency
125MHz 100MHz 100MHz
Internal Bank
Ref.
Power
SDRAM Package
Plating
4 Banks
4K
Normal
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/Nov. 01 2
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PC100 SDRAM Unbuffered DIMM
HYM71V16655BT8 Series
PIN DESCRIPTION
PIN CK0~CK3 CKE0 /S0, /S2 BA0, BA1 A0 ~ A11 /RAS, /CAS, /WE DQM0~DQM7 DQ0 ~ DQ63 VCC VSS SCL SDA SA0~2 WP NC PIN NAME Clock Inputs Clock Enable Chip Select SDRAM Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground SPD Clock Input SPD Data Input/Output SPD Address Input Write Protect for SPD No Connection DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CK, CKE and DQM Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9 Auto-precharge flag : A10 /RAS, /CAS and /WE define the operation Refer function truth table for details Controls output buffers in read mode and masks inp.