MC8051

www.DataSheet4U.com Design & Consulting GesmbH MC8051 IP Core Synthesizeable VHDL Microcontroller IP-Core User Guide Web: http://oregano.at/services/8051.htm Contact: [email protected] Version 1.1 June 2002 www.DataSheet4U.com 8051 IP Core - Overview Key Features Fully synchronous design Instruction set compatible to the industry standard 8051 microcontroller Optimized architecture enables fast one to four clocks per OP code Up to 10 times faster due to completely new architecture User selectable number of timers/counters as well as serial interface units Active timer/counter and serial interface units selectable via additional special function register Optional implementation of the multiply command (MUL) using a parallel multiplier unit Optional implementation of the divide command (DIV) using a parallel divider unit Optional implementation of the decimal adjustment command (DA) No multiplexed I/O ports 256 bytes internal RAM Up to 64 Kbytes ROM and up to 64 Kbytes RAM Source code available free of charge under the GNU LGPL license Technology independent, clear structured, well commented VHDL source code Easily expandable by adapting/changing VHDL source code Parameterizeable via VHDL constants page 2 of 11 www.DataSheet4U.com 8051 IP Core – Block Diagram The starting from the top level module and its submodules are depicted in figure 1. The toplevel signal names are shown as well as the three memory blocks used in the design. The user selectable number of serial ...