GS864036T-xxxV

www.DataSheet4U.com Preliminary GS864018/32/36T-xxxV 100-Pin TQFP Commercial Temp Industrial Temp Features 4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs 250 MHz–167 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O FT pin for user-configurable flow through or pipeline operation Single Cycle Deselect (SCD) operation 1.8 V or 2.5 V core power supply 1.8 V or 2.5 V I/O supply LBO pin for Linear or Interleaved Burst mode Internal input resistors on mode pins allow floating mode pins Default to Interleaved Pipeline mode Byte Write (BW) and/or Global Write (GW) operation Internal self-timed write cycle Automatic power-down for portable applications JEDEC-standard 100-lead TQFP package RoHS-compliant 100-lead TQFP package available cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Dat...