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K8A5615ET(B)A
FLASH MEMORY
Document Title 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash Memory Revision History
Revision No. History
0.0 0.1 Advanced Revision - Change the speed code 7B : 90ns @54MHz ---> 7B : 88.5ns @54MHz Revision - Change the device version ID Top boot device : 22ECH --> 22FCH Bottom boot device : 22EDH --> 22FDH - Not support accelerated quad word program operation Revision - Change the initial access time of asynchronous read mode K8A56156ET(B)A-DE7C tAA : 70ns--->80ns tCE : 70ns--->80ns - Support accelerated quad word program operation Revision - Add the operation flow chart Revision - Add the description of range limitation of data read out during program suspend.(Refer to "Program Suspend/Resume" paragragh)
Draft Date
March 15, 2004 June 1, 2004
Remark
Advance Preliminary
0.2
July 5, 2004
Preliminary
0.3
August 3, 2004
Preliminary
0.4
August 23, 2004
Preliminary
0.5
September 6, 2004 Preliminary
0.6
Revision December 13, 2004 Preliminary - Add the requirement and note of Quadruple word program operation Specification finalized December 16, 2004
1.0
1
Revision 1.0 December, 2004
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K8A5615ET(B)A
FLASH MEMORY
256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash Memory
FEATURES
• Single Voltage, 1.7V to 1.95V for Read and Write operations • Organization - 16,772,216 x 16 bit ( Word Mode Only) • Read While Program/Erase Operation • Multiple Bank Architecture - 16 Banks (16Mb Partition) • OTP Block : Extra 256Byte block • Read Access Time (@ CL=30pF) - Asynchronous Random Access Time : 90ns (54MHz) / 80ns (66MHz) - Synchronous Random Access Time : 88.5ns (54MHz) / 70ns (66MHz) - Burst Access Time : 14.5ns (54MHz) / 11ns (66MHz) • Burst Length : - Continuous Linear Burst - Linear Burst : 8-word & 16-word with No-wrap & Wrap • Block Architecture - Eight 4Kword blocks and five hundreds eleven 32Kword blocks - Bank 0 contains eight 4 Kword blocks and thirty-one 32Kword blocks - Bank 1 ~ Bank 15 contain four hundred eighty 32Kword blocks • Reduce program time using the VPP • Support Single & Quad word accelerate program • Power Consumption (Typical value, CL=30pF) - Burst Access Current : 30mA - Program/Erase Current : 15mA - Read While Program/Erase Current : 40mA - Standby Mode/Auto Sleep Mode : 25uA • Block Protection/Unprotection - Using the software command sequence - Last two boot blocks are protected by WP=VIL - All blocks are protected by VPP=VIL • Handshaking Feature - Provides host system with minimum latency by monitoring RDY • Erase Suspend/Resume • Program Suspend/Resume • Unlock Bypass Program/Erase • Hardware Reset (RESET) • Data Polling and Toggle Bits - Provides a software method of detecting the status of program or erase completion • Endurance 100K Program/Erase Cycles Minimum • Data Retention : 10 years • Extended Temperature : -25°C ~ 85°C • Support Common Flash Memory Interface • Low Vcc Write Inhibit • Package : TBD
GENERAL DESCRIPTION
The K8A5615E featuring single 1.8V power supply is a 256Mbit Synchronous Burst Multi Bank Flash Memory organized as 16Mx16. The memory architecture of the device is designed to divide its memory arrays into 519 blocks with independent hardware protection. This block architecture provides highly flexible erase and program capability. The K8A5615E NOR Flash consists of sixteen banks. This device is capable of reading data from one bank while programming or erasing in the other bank. Regarding read access time, the K8A5615E provides an 14.5ns burst access time and an 88.5ns initial access time at 54MHz. At 66MHz, the K8A5615E provides an 11ns burst access time and 70ns initial access time. The device performs a program operation in units of 16 bits (Word) and an erase operation in units of a block. Single or multiple blocks can be erased. The block erase operation is completed within typically 0.7 sec. The device requires 15mA as program/erase current in the extended temperature ranges. The K8A5615E NOR Flash Memory is created by using Samsung's advanced CMOS process technology.
PIN DESCRIPTION
Pin Name A0 - A23 DQ0 - DQ15 CE OE RESET VPP WE WP CLK RDY AVD Vcc VSS Pin Function Address Inputs Data input/output Chip Enable Output Enable Hardware Reset Pin Accelerates Programming Write Enable Hardware Write Protection Input Clock Ready Output Address Valid Input Power Supply Ground
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 1.0 December, 2004
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K8A5615ET(B)A
FUNCTIONAL BLOCK DIAGRAM
FLASH MEMORY
Bank 0 Address Vcc Vss Vpp CLK CE OE WE WP RESET RDY AVD I/O Interface & Bank Control Bank 1 Address
X Dec
Bank 0 Cell Array
Y Dec
Latch & Control
Y Dec
X Dec Bank 1 Cell Array
Latch & Control
Bank 15 Address
X Dec
Bank 15 Cell Array
Y Dec
A0~A23 DQ0~ DQ15 Erase Control Block Inform
Latch & Control
Program Control
High Voltage Gen.
3
Revision 1.0 December, 2004.