K8A5615ETA

www.DataSheet4U.com K8A5615ET(B)A FLASH MEMORY Document Title 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash Memory Revision History Revision No. History 0.0 0.1 Advanced Revision - Change the speed code 7B : 90ns @54MHz ---> 7B : 88.5ns @54MHz Revision - Change the device version ID Top boot device : 22ECH --> 22FCH Bottom boot device : 22EDH --> 22FDH - Not support accelerated quad word program operation Revision - Change the initial access time of asynchronous read mode K8A56156ET(B)A-DE7C tAA : 70ns--->80ns tCE : 70ns--->80ns - Support accelerated quad word program operation Revision - Add the operation flow chart Revision - Add the description of range limitation of data read out during program suspend.(Refer to "Program Suspend/Resume" paragragh) Draft Date March 15, 2004 June 1, 2004 Remark Advance Preliminary 0.2 July 5, 2004 Preliminary 0.3 August 3, 2004 Preliminary 0.4 August 23, 2004 Preliminary 0.5 September 6, 2004 Preliminary 0.6 Revision December 13, 2004 Preliminary - Add the requirement and note of Quadruple word program operation Specification finalized December 16, 2004 1.0 1 Revision 1.0 December, 2004 www.DataSheet4U.com K8A5615ET(B)A FLASH MEMORY 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash Memory FEATURES Single Voltage, 1.7V to 1.95V for Read and Write operations Organization - 16,772,216 x 16 bit ( Word Mode Only) Read While Program/Erase Operation Multiple Bank Architecture - 16 Banks (16M...