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CX099 Dataheets PDF



Part Number CX099
Manufacturers Sony
Logo Sony
Description ICX099AL
Datasheet CX099 DatasheetCX099 Datasheet (PDF)

www.DataSheet4U.com ICX099AL 1/2-inch Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras For the availability of this product, please contact the sales office. Description The ICX099AL is a 1/2-inch optical interline CCD solid-state image sensor with a square pixel array and 800K effective pixels. Progressive scan allows all pixels' signals to be output independently within approximately 1/15 second. Also, the adoption of high-speed mode supports 30 frames per second. This chi.

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www.DataSheet4U.com ICX099AL 1/2-inch Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras For the availability of this product, please contact the sales office. Description The ICX099AL is a 1/2-inch optical interline CCD solid-state image sensor with a square pixel array and 800K effective pixels. Progressive scan allows all pixels' signals to be output independently within approximately 1/15 second. Also, the adoption of high-speed mode supports 30 frames per second. This chip features an electronic shutter with variable charge-storage time which makes it possible to realize high resolution, full-frame still image without a mechanical shutter. Further, high sensitivity and low dark current are achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. This chip is suitable for applications such as high resolution cameras for FA, etc. Features • Progressive scan allows individual readout of the image signals from all pixels. • High horizontal and vertical resolution still image without a mechanical shutter. • Supports 30 frames per second mode • Square pixel • Horizontal drive frequency: 14.31818MHz • No voltage adjustments (reset gate and substrate bias are not adjusted.) • High resolution, high sensitivity, low dark current • Continuous variable-speed shutter • Low smear • Excellent antiblooming characteristics Device Structure • Interline CCD image sensor • Optical size: • Number of effective pixels: • Total number of pixels: • Chip size: • Unit cell size: • Optical black: • Number of dummy bits: • Substrate material: 20 pin DIP (Cer-DIP) Pin 1 2 V 7 3 Pin 11 H 40 Optical black position (Top View) 1/2-inch format 1034 (H) × 779 (V) approx. 800K pixels 1077 (H) × 788 (V) approx. 850K pixels 7.60mm (H) × 6.20mm (V) 6.25µm (H) × 6.25µm (V) Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction: Front 7 pixels, rear 2 pixels Horizontal 29 Vertical 1 Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97747-PS www.DataSheet4U.com ICX099AL Block Diagram and Pin Configuration (Top View) GND VOUT GND Vφ2B Vφ2A 2 Vφ3 10 9 8 7 6 NC 5 4 3 Vertical register Vφ1 1 Note) NC NC Horizontal register Note) : Photo sensor 11 12 13 14 15 16 17 18 19 20 GND φSUB CSUB φRG VDD Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol Vφ1 Vφ2A NC Vφ2B NC Vφ3 GND GND NC VOUT Signal output Description Pin No. 11 12 13 Symbol VDD GND φSUB CSUB NC NC VL φRG Hφ1 Hφ2 Hφ 1 Hφ 2 NC NC VL Description Supply voltage GND Substrate clock Substrate bias∗1 Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock 14 15 Vertical register transfer clock GND GND 16 17 18 19 20 Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock ∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF. Absolute Maximum Ratings Item VDD, VOUT, φRG – φSUB Vφ2A, Vφ2B – φSUB Against φSUB Vφ1, Vφ3, VL – φSUB Hφ1, Hφ2, GND – φSUB CSUB – φSUB VDD, VOUT, φRG, CSUB – GND Against GND Vφ1, Vφ2A, Vφ2B, Vφ3 – GND Hφ1, Hφ2 – GND Against VL Vφ2A, Vφ2B – VL Vφ1, Vφ3, Hφ1, Hφ2, GND – VL Voltage difference between vertical clock input pins Between input Hφ1 – Hφ2 clock pins Hφ1, Hφ2 – Vφ3 Storage temperature Operating temperature ∗2 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. –2– Ratings –40 to +10 –50 to +15 –50 to +0.3 –40 to +0.3 –25 to –0.3 to +18 –10 to +18 –10 to +5 –0.3 to +28 –0.3 to +15 to +15 –5 to +5 –13 to +13 –30 to +80 –10 to +60 Unit V V V V V V V V V V V V V °C °C ∗2 Remarks www.DataSheet4U.com ICX099AL Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock Symbol VDD VL φSUB φRG Min. 14.55 Typ. 15.0 ∗1 ∗2 ∗2 Max. 15.45 Unit V Remarks ∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. DC Characteristics Item Supply current Symbol IDD Min. Typ. 6.0 Max. Unit mA Remarks Clock Voltage Conditions Item Readout clock voltage VVT VVH02A VVH1, VVH2A, VVH2B, VVH3 VVL1, VVL2A, VVL2B, VVL3 Vertical transfer clock voltage Vφ1, Vφ2A, Vφ2B, Vφ3 | VVL1 – VVL3 | VVHH VVHL VVLH VVLL Horizontal transfer clock voltage Reset gate clock voltage Substrate clock voltage VφH VHL VφRG VRGLH – VRGLL VRGL – VRGLm VφSUB 19.75 20.5 4.75 –0.05 3.0 5.0 0 3.3 Symbol Min. 14.55 –0.05 –0.2 –5.8 5.


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