(CY7C147xV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
Description
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PRELIMINARY
CY7C1471V25 CY7C1473V25 CY7C1475V25
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture
Features
No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. Can support up to 133-MHz bus operations with zero wait states Data is transferred on every clock Pin com...
