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DS25CP104 Dataheets PDF



Part Number DS25CP104
Manufacturers National Semiconductor
Logo National Semiconductor
Description 3.125 Gbps 4x4 LVDS Crosspoint Switch
Datasheet DS25CP104 DatasheetDS25CP104 Datasheet (PDF)

www.DataSheet4U.com August 2007 DS25CP104 3.125 Gbps 4x4 LVDS Crosspoint Switch with PE and EQ DS25CP104 3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit Pre-Emphasis and Receive Equalization General Description The DS25CP104 is a 3.125 Gbps 4x4 LVDS crosspoint switch optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. The non-blocki.

  DS25CP104   DS25CP104


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www.DataSheet4U.com August 2007 DS25CP104 3.125 Gbps 4x4 LVDS Crosspoint Switch with PE and EQ DS25CP104 3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit Pre-Emphasis and Receive Equalization General Description The DS25CP104 is a 3.125 Gbps 4x4 LVDS crosspoint switch optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. The non-blocking architecture allows connections of any input to any output or outputs. The switch configuration can be accomplished via external pins or the System Management Bus (SMBus) interface. The DS25CP104 features four levels (Off, Low, Medium, High) of transmit pre-emphasis (PE) and four levels (Off, Low, Medium, High) of receive equalization (EQ) settable via the SMBus interface. Off and Medium PE levels and Off and Low EQ levels are settable with the external pins. In addition, the SMBus circuitry enables the loss of signal (LOS) monitors that can inform a system of the presence of an open inputs condition (e.g. disconnected cable). Wide input common mode range allows the switch to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. Each differential input and output is internally terminated with a 100Ω resistor to lower device insertion and return losses, reduce component count and further minimize board space. Features ■ DC - 3.125 Gbps low jitter, low skew, low power operation ■ Pin and SMBus configurable, fully differential, nonblocking architecture ■ Pin (two levels) and SMBus (four levels) selectable preemphasis and equalization eliminate ISI jitter to CML and LVPECL drivers ■ Wide Input Common Mode Range enables easy interface ■ LOS circuitry detects open inputs fault condition ■ On-chip 100Ω input and output termination minimizes insertion and return losses, reduces component count and minimizes board space ■ 8 kV ESD on LVDS I/O pins protects adjoining components ■ Small 6 mm x 6 mm LLP-40 space saving package Applications ■ ■ ■ ■ SD/HD/3GHD SDI Routers OC-48 / STM-16 Fibre Channel (2GFC) InfiniBand and FireWire Typical Application 30003703 © 2007 National Semiconductor Corporation 300037 www.national.com DS25CP104 www.DataSheet4U.com Ordering Code NSID DS25CP104TSQ Function Crosspoint Switch Available Equalization Levels Off / Low / Medium / High Available Pre-Emphasis Levels Off / Low / Medium / High Block Diagram 30003701 Pin Diagram 30003702 DS25CP104 Pin Diagram www.national.com 2 www.DataSheet4U.com DS25CP104 Pin Descriptions Pin Name IN0+, IN0- , IN1+, IN1-, IN2+, IN2-, IN3+, IN3OUT0+, OUT0-, OUT1+, OUT1-, OUT2+, OUT2-, OUT3+, OUT3EQ0, EQ1, EQ2, EQ3 PE0, PE1, PE2, PE3 EN_smb Pin Number 1, 2, 4, 5, 6, 7, 9, 10 29, 28, 27, 26, 24, 23, 22, 21 40, 39, 11, 12 31, 20, 19, 18 17 I/O, Type I, LVDS Pin Description Inverting and non-inverting high speed LVDS input pins. O, LVDS Inverting and non-inverting high speed LVDS output pins. I, LVCMOS I, LVCMOS I, LVCMOS Receive equalization level select pins. These pins are functional regardless of the EN_smb pin state. Transmit pre-emphasis level select pins. These pins are functional regardless of the EN_smb pin state. System Management Bus (SMBus) enable pin. The pin has an internal pull down. When the pin is set to a [1], the device is in the SMBus mode. All SMBus registers are reset when this pin is toggled. There is a 20k pulldown device on this pin. For EN_smb = [0], these pins select which LVDS input is routed to the OUT0. In the SMBus mode, when the EN_smb = [1], these pins are SMBus clock input and data input pins respectively. For EN_smb = [0], these pins select which LVDS input is routed to the OUT1. In the SMBus mode, when the EN_smb = [1], these pins are the User-Set SMBus Slave Address inputs. For EN_smb = [0], these pins select which LVDS input is routed to the OUT2. In the SMBus mode, when the EN_smb = H, these pins are the User-Set SMBus Slave Address inputs. For EN_smb = [0], these pins select which LVDS input is routed to the OUT3. In the SMBus mode, when the EN_smb = [1], these pins are nonfunctional and should be tied to either logic H or L. For EN_smb = [0], this is the power down pin. When the PWDN is set to a [0], the device is in the power down mode. The SMBus circuitry can still be accessed provided the EN_smb pin is set to a [1]. In the SMBus mode, the device is powered up by either setting the PWDN pin to [1] OR by writing a [1] to the Control Register D[7] bit ( SoftPWDN). The device will be powered down by setting the PWDN pin to [0] AND by writing a [0] to the Control Register D[7] bit ( SoftPWDN). Power supply pins. Ground pin and a pad (DAP - die attach pad). S00/SCL S01/SDA 37 36 I, LVCMOS I/O, LVCMOS S10/ADDR0, S11/ADDR1 35, 34 I, LVCMOS S20/ADDR2, S21/AD.


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