NS16550A

www.DataSheet4U.com Accessing the NS16550A UART in the PS 2 Model 50 60 70 and 80 Accessing the NS16550A UART in the PS 2 Model 50 60 70 and 80 INTRODUCTION This paper reviews fundamental concepts of the Micro Channel Architecture and their relation to the NS16550A UART All 4 of the PS 2 personal computers reviewed use the NS16550A for asynchronous serial communication The first part is an overview of the PS 2 system board and Micro Channel Architecture (MCA) in the Models 50 60 70 and 80 personal computers The next part explains the basic configuration and system initialization procedures for the UART that occur after power-up The last part describes the overall interrupt procedure and the advantages of using the on-chip FIFOs of the NS16550A These explanations describe the CPU accesses to the UART via MCA Timing diagrams in the appendix show these accesses to the UART OVERVIEW OF THE PS 2 MODEL 50 60 70 AND 80 SYSTEM ARCHITECTURE The block diagram indicates a number of identical functions that all system boards have (Figure 1) Each system CPU has an 8 channel DMA Controller and an optional math coprocessor associated with it via the local bus The DMA Controller emulates the dual 8237 DMA controllers found on the IBM AT Additionally this DMA Controller provides Extended and Virtual Mode operation These modes allow it to interface with various DMA slave devices and the CPU to dynamically select the arbitration level for 2 of the DMA channels A central arbitration point allo...