If CE and OE are LOW and WE and NE are HIGH at
the end of the cycle, a READ will be performed and the
outputs will go active, indicating the end of the STORE.
Hardware Nonvolatile RECALL
A RECALL cycle is performed when CE, OE and NE
are LOW while WE is HIGH. Like the STORE cycle,
RECALL is initiated when the last of the three clock-
signals goes to the RECALL state. Once initiated, the
RECALL cycle will complete, during which all inputs
are ignored. When the RECALL completes, any READ
or WRITE state on the input pins will take effect.
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL in no way alters the data in the nonvolatile
cells. The nonvolatile data can be recalled an unlimited
number of times.
Like the STORE cycle, a transition must occur on some
control pins to cause a RECALL, preventing inadvert-
Automatic Power Up RECALL
On power up, once VCC exceeds the sense voltage of
VSWITCH, a RECALL cycle is automatically initiated.
The voltage on the VCC pin must not drop below
VSWITCH once it has risen above it in order for the
RECALL to operate properly. Due to this automatic
RECALL, SRAM operation cannot commence until
tRESTORE after VCC exceeds VSWITCH. If the X20CZ16
is in a WRITE state at the end of power up RECALL,
the SRAM data will be corrupted.
To help avoid this situation, a 10 KΩ resistor should be
connected between WE and system VCC.
The X20CZ16 offers two levels of protection to sup-
press inadvertent STORE cycles. If the control signals
(CE, OE, WE and NE) remain in the STORE condition
at the end of a STORE cycle, a second STORE cycle
will not be started. The STORE (or RECALL) will be ini-
tiated only after a transition on any one of these signals
to the required state. In addition to multi-trigger protec-
tion, the X20CZ16 offers hardware protection through
VCC Sense. When VCC < VSWITCH the externally initi-
ated STORE operation will be inhibited.
Low Average Active Power
The X20CZ16 has been designed to draw signiﬁcantly
less power when WE is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When WE is HIGH the chip consumes only standby
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. The time during which the chip is disabled (CE
3. The cycle time for accesses (CE LOW)
4. The ratio of READs to WRITEs
5. The operating temperature
6. The VCC level
REV 1.4.2 10/3/03
Characteristics subject to change without notice. 12 of 14