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MT48H16M16LF Dataheets PDF



Part Number MT48H16M16LF
Manufacturers Micron Technology
Logo Micron Technology
Description (MT48H16M16LF / MT48H16M32LF) 16 Meg x 32 Mobile SDRAM
Datasheet MT48H16M16LF DatasheetMT48H16M16LF Datasheet (PDF)

www.DataSheet4U.com 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Features Mobile SDRAM MT48H32M16LF – 8 Meg x 16 x 4 banks MT48H16M32LF/LG – 4 Meg x 32 x 4 banks Features • Endur-IC™ technology • Fully synchronous; all signals registered on positive edge of system clock • VDD = 1.7–1.95V; VDDQ = 1.7–1.95V • Internal, pipelined operation; column address can be changed every clock cycle • Four internal banks for concurrent operation • Programmable burst lengths: 1, 2, 4, 8, and continuous1 • Au.

  MT48H16M16LF   MT48H16M16LF



Document
www.DataSheet4U.com 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Features Mobile SDRAM MT48H32M16LF – 8 Meg x 16 x 4 banks MT48H16M32LF/LG – 4 Meg x 32 x 4 banks Features • Endur-IC™ technology • Fully synchronous; all signals registered on positive edge of system clock • VDD = 1.7–1.95V; VDDQ = 1.7–1.95V • Internal, pipelined operation; column address can be changed every clock cycle • Four internal banks for concurrent operation • Programmable burst lengths: 1, 2, 4, 8, and continuous1 • Auto precharge, includes concurrent auto precharge • Auto refresh and self refresh modes • LVTTL-compatible inputs and outputs • On-chip temperature sensor to control refresh rate • Partial-array self refresh (PASR) • Deep power-down (DPD) • Selectable output drive (DS) Table 1: DQ Bus Width Options • VDD/VDDQ – 1.8V/1.8V • Row size option – Standard addressing option – Reduced page-size option • Configuration – 32 Meg x 16 (8 Meg x 16 x 4 banks) – 16 Meg x 32 (4 Meg x 32 x 4 banks) • Plastic “green” packages – 54-Ball VFBGA (10mm x 11.5mm) – 90-Ball VFBGA (10mm x 13mm) • Timing – cycle time – 7.5ns at CL = 3 – 8ns at CL = 3 • Power – Standard IDD2P/IDD7 – Low IDD2P/IDD7 • Operating temperature range – Commercial (0°C to +70°C) – Industrial (–40°C to +85°C) • Design revision Marking H LF LG3, 4 32M16 16M32 CJ5 CM3 -75 -8 None L None IT :A Configuration Addressing JEDECStandard Option 4 BA0, BA1 A0–A12 A0–A9 A0–A12 A0–A8 Reduced Page-Size Option2 4 BA0, BA1 – – A0–A13 A0–A7 Architecture Number of banks Bank address balls Row address balls Column address balls Row address balls Column address balls x16 x32 Table 2: Key Timing Parameters CL = CAS (READ) latency Clock Rate (MHz) CL = 2 104 100 CL = 3 133 125 Access Time CL = 2 9ns 9ns CL = 3 6ns 7ns Notes: 1. For continuous page burst, contact factory for availability. 2. For reduced page-size option, contact factory for availability. 3. LG is a reduced page-size option. Contact factory for availability. 4. Only available for x32 configuration. 5. Only available for x16 configuration. Speed Grade -75 -8 PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. H 6/07 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Extended Mode Register (EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


MT48H16M32LG MT48H16M16LF MTD5P06V


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