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IDT74SSTUBF32865A Dataheets PDF



Part Number IDT74SSTUBF32865A
Manufacturers IDT
Logo IDT
Description 28-BIT 1:2 REGISTERED BUFFER
Datasheet IDT74SSTUBF32865A DatasheetIDT74SSTUBF32865A Datasheet (PDF)

www.DataSheet4U.com DATASHEET 28-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTUBF32865A The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW). Description This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All cloc.

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www.DataSheet4U.com DATASHEET 28-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTUBF32865A The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW). Description This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The IDT74SSTUBF32865A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low. The device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the IDT74SSTUBF32865A must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when both DCS0 and DCS1 are high. If either DCS0 and DCS1 input is low, the Qn outputs will function normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs low and the PTYERR output high. If the DCS-control functionality is not desired, then the CSGateEnable input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs. Features • 28-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs • • • and outputs Supports LVCMOS switching levels on CSGateEN and RESET inputs Low voltage operation: VDD = 1.7V to 1.9V Available in 160-ball LFBGA package Applications • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS98ULPA877A or IDTCSPUA877A • Ideal for DDR2 400, 533, 667, and 800 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 1 IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Block Diagram (CS ACTIVE) VREF PARIN D R Q 22 PARITY GENERATOR AND CHECKER PTYERR Q0A D0 D R Q Q0B Q21A D21 D R Q Q21B QCS0A DCS0 D R CSGateEN QCS1A DCS1 D R Q QCS1B Q QCS0B DCKE0, DCKE1 QCKE0A, QCKE1A 2 D R Q 2 QCKE0B, QCKE1B QODT0A, QODT1A DODT0, DODT1 2 D R Q 2 QODT0B, QODT1B RESET CLK CLK 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 2 IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Pin Configuration 1 A 2 3 4 5 6 7 8 9 10 11 12 1 A VREF D1 D3 D6 D7 D11 D18 CSGate EN CLK CLK RESET D0 D17 D19 D13 DODT1 DCKE0 VREF 2 NC D2 D4 D5 D8 D9 D12 D15 DCS0 DCS1 D14 D10 D16 D21 D20 DODT0 DCKE1 MCL 3 PARIN NC 4 NC NC 5 NC NC 6 QCKE1A 7 QCKE0A 8 Q21A Q21B 9 Q19A Q19B 10 Q18A Q18B 11 Q17B QODT0B QODT1B 12 Q17A QODT0A QODT1A Q20A Q16A Q1A Q2A Q5A QCS0A QCS1A Q6A Q10A Q9A Q11A Q15A Q14A Q8B Q8A B C D E F G H J K L M N P R T U V B C D E F G H J K L M N P R T U V QCKE1B QCKE0B VDDL VDDL VDDL VDDL VDDL GND VDDL GND GND VDDL GND GND GND GND GND GND GND GND VDDL GND GND VDDL VDDL VDDL NC VDDL NC VDDR GND GND VDDR VDDR GND VDDR GND VDDR GND VDDR GND GND VDDR VDDR GND VDDR GND VDDR GND VDDR GND GND Q20B Q16B Q1B Q2B Q5B QCS0B QCS1B Q6B Q10B Q9B Q11B Q15B Q14B VDDL VDDL VDDR GND VDDR GND MCL MCL PTYERR NC MCH MCH Q3B Q3A Q12B Q12A Q7B Q7A Q4B Q4A Q13B Q13A Q0B Q0A 160-Ball BGA TOP VIEW NOTE: 1. An empty cell indicates no ball is populated at that gridpoint. NC denotes a no-connect (ball present but not connected to the die). MCL denotes a pin that Must be Connected LOW. MCH denotes a pin that Must be Connected HIGH. 160-Ball BGA TOP VIEW 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 3 IDT7.


IDT74SSTUB32866B IDT74SSTUBF32865A IDT74SSTUBF32866B


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