IDT74SSTUAE32866A

www.DataSheet4U.com DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 IDT74SSTUAE32866A outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS and CSR input is low, the Qn outputs will function normally. The RESET input has priority over the DCS and CSR control and will force the outputs low. If the DCS-control functionality is not desired, then the CSR input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC). Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.425V to 1.575V VDD operation. The control inputs are LVCMOS. All outputs are 1.5-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. IDT74SSTUAE32866A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). A - Pair Configuration (C01 = 0, C11 = 1 and C02 = 0, C12 = 1) Parity that arrives one cycle after the data input to which it applies is checked on the PAR_IN of the first regi...