IDT70P3517

www.DataSheet4U.com 512K/256K x36 SYNCHRONOUS DUAL QDR-IITM ® PRELIMINARY DATASHET IDT70P3537 IDT70P3517 Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ 18Mb Density (512K x 36) – Also available 9Mb Density (256K x 36) QDR-II x 36 Burst-of-2 Interface – Commercial: 233MHz, 250MHz Two independent ports – True Dual-Port Access to common memory Separate, Independent Read and Write Data Buses on each Port – Supports concurrent transactions Two-Word Burst on all DPRAM accesses DDR (Double Data Rate) Multiplexed Address Bus – One Read and One Write request per clock cycle DDR (Double Data Rate) Data Buses – Four word burst data (Two Read and Two Write) per clock on ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ each port – Four word transfers each of Read & Write per clock cycle per port (four word bursts on 2 ports) Octal Data Rate Port Enable pins (E0,E1) for depth expansion Dual Echo Clock Output with DLL-based phase alignment High Speed Transceiver Logic inputs – scaled to receive signals from 1.4V to 1.9V Scalable output drivers – Drives HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V – Output impedance adjustable from 35 ohms to 70 ohms 1.8V Core Voltage (VDD) 576-ball Flip Chip BGA (25mm x 25mm, 1.0mm ball pitch) JTAG Interface - IEEE 1149.1 Compliant Functional Block Diagram VREFL EP[1:0] EL[1:0] WRITE REGISTER WRITE REGISTER VREFR ER[1:0] D0 L - D3 5 L KL KL LEFT PORT DATA REGISTER AND LOGIC KL ZQL (1) Q0 L - Q3 5 L CQL, CQL WRITE DRIVER RIGHT PORT DATA REGISTER AND LOGIC KR SELECT OUTPUT D0 R - D3 5 R KR ...