ICSSSTUB32866B

www.DataSheet4U.com Integrated Circuit Systems, Inc. ICSSSTUB32866B Advance Information 25-Bit Configurable Registered Buffer for DDR2 Recommended Application: DDR2 Memory Modules Provides complete DDR DIMM solution with ICS97ULP877 Ideal for DDR2 400,533,667 and 800 Product Features: 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality Supports SSTL_18 JEDEC specification on data inputs and outputs Supports LVCMOS switching levels on CSR and RESET inputs Low voltage operation VDD = 1.7V to 1.9V Available in 96 BGA package Drop-in replacement for ICSSSTUA32864 Green packages available Pin Configuration 1 A B C D E F G H J K L M N P R T 2 3 4 5 6 Functionality Truth Table Inputs RST H H H H H H H H H H H H L DCS CSR Dn, DODT, DCKE ↑ ↓ L ↑ ↓ H L or H L or H X ↑ ↓ L ↑ ↓ H L or H L or H X ↑ ↓ L ↑ ↓ H L or H L or H X ↑ ↓ L ↑ ↓ H L or H L or H X X or X or X or Floating Floating Floating CK CK Outputs, QCS L L Q0 L L Q0 H H Q0 H H Q0 L 96 Ball BGA (Top View) Qn L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L QODT, QCKE L H Q0 L H Q0 L H Q0 L H Q0 L L L L L L L L H L H L H H L H L H L H H H H H H X or X or Floating Floating 1165—10/25/06 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their...