RNA50C27AUS

www.DataSheet4U.com RNA50C27AUS CMOS System-Reset IC REJ03D0834-0100 Preliminary Rev.1.00 Apr 10, 2006 Description This IC facilitates complicated power-on and power-monitoring resets of microcomputers that require the 3.3-V and 1.8-V dual power supplies. It also facilitates change of delay time of reset signal by externally setting resistance and capacity for delay time. By employing complementary open-drain output, desired output such as open-drain output and CMOS output can be obtained. Functions 3.3-V detection voltage Accuracy of 3.3-V detection voltage Hysteresis of 3.3-V detection voltage Open-drain/CMOS output 1.8-V PMOS drive output Ultra-small SSOP-8 package : 2.7 V : ±1.0% : 5% Typ. Block Diagram MR 8 VDD33 1 – + CRext 7 2 RESP Delay 3 RESN Vref VDD18 6 5 SWG GND 4 Rev.1.00 Apr 10, 2006 page 1 of 7 RNA50C27AUS Pin Arrangement VDD33 RESP RESN GND 1 2 3 4 (Top view) 8 7 6 5 MR CRext VDD18 SWG Pin Description Pin No. 1 2 3 4 5 6 7 Pin Name VDD33 RESP RESN GND SWG VDD18 CRext Function Input power supply pin for 3.3-V voltage. Recommended operating range is 2.7 to 3.6 V. Set the input voltage to 0.033 V/µs or less when starting up. Active-low reset signal output pin. By connecting to RESN pin, CMOS output can be used. If using open-drain, please connect pull-down resistor. Active-low reset signal output pin. By connecting to RESP pin, CMOS output can be used. If using open-drain, please connect pull-up resistor. GND pin External PMOS gate control ...