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R2A20111SP/DD
Power Factor Correction Controller IC
REJ03F0231-0100 Rev.1.00 Mar 28, 2007
Description
The R2A20111 is a power-factor correction (PFC) controller IC. This IC adopts continuous conduction mode as PFC operation. Various functions such as constant power limit, overvoltage detection, overcurrent detection, soft start, feedback-loop disconnection detection, and holding function of PFC operation through momentary outage (PFC hold function) are incorporated in a single chip. These functions reduce external circuitry. The constant power limit function allows to eliminate a significant amount of coil noise which is generated due to overcurrent detection operation in case of conventional overload. The PFC hold function enables quick recovery by continuing PFC operation after momentary outage. The hold time can be adjusted by an external capacitance. Overcurrent detection pin is separately provided. Latch mode shutdown function is incorporated. A soft-start control pin provides for the easy adjustment of soft-start operation, and can be used to prevent overshooting of the output voltage.
Features
• Maximum ratings ⎯ Power-supply voltage Vcc: 24 V ⎯ Operating junction temperature Tjopr: – 40 to 125°C • Electrical characteristics ⎯ VREF output voltage VREF: 5.0 V ± 3% ⎯ UVLO operation start voltage VH: 10.5 ± 0.9 V ⎯ UVLO operation stop voltage VL: 9.0 ± 0.7 V ⎯ PFC output maximum ON duty Dmax-out: 95% (typ.) • Functions ⎯ Constant power limit function ⎯ Continuous conduction mode ⎯ Hold function of PFC operation on momentary outage (PFC hold function) ⎯ Overvoltage detection ⎯ Overcurrent detection ⎯ Soft start ⎯ Feedback loop disconnection detection ⎯ IC shutdown function ⎯ Package lineup: SOP-16 and DILP-16
Applications
• • • • Flat panel display Projector Desktop PC White goods
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 1 of 40
R2A20111SP/DD
Ordering Information
Part No. R2A20111SPW0 R2A20111DDU0 Package Name FP-16DAV DP-16FV Package Code PRSP0016DH-B PRDP0016AE-B Taping Spec. 2000 pcs./one taping product —
System Diagram
Rec+
150 μH
B+
680k To FB 680k B+ OUT (385V dc)
T1
Q1 Rec–
From OUT 470μF ×2 (450V)
from auxiliary
24V 4.7μ
VRB1
GND
VCC
16
62k
RT 9
VREF
5V Internal Bias
3.6V 0.65V
H
10.5V
27.5V
L 9.0V
UVLO
5V VREF Generator
6
VREF In GOOD Out
VREF
0.1μ
CT 10
390p
Reset: Vcc<4V Shut down
R S
Q Q
UVL
R
Q Q
Gate Driver +/– 1.0A (PEAK)
VREF CAO 6800p 2.2k
S
7
470p 82k
Imo = K × {IAC × (VEO – 1V)}
To Q1 gate
R S
Q Q
1
OUT
DELAY RESET
VREF
SS
IAC
CAMP
12
1.28M
1000p
IAC
VE O
IMO
VREF
K
CAI
2.4k VREF 22k 100
RT
5
PFC DELAY
3
1.2V
DELAY
0.22μ
CLIMIT
10k 0.0165 (5W) 2.4k 100p
CLIMIT
Shut down
8
1.3V
4.0V
CGND EO
4
Gain
RT
820k
14
2.5V
VREF
VREF
0.033μ
VAMP FB 13
2.688V 2.638V
15
B+OVP 25μA
0.47μ
SS
From VRB1(B+ monitor1)
S Q
FB LOW
0.52V 720k
R Q
2
PFC-OFF
GND
PFC-ON
1μ
11
0.1 μ
Circuit Ground
14k
0.82V 0.79V
VREF GOOD
IN OUT PFC DELAY
S R
Q Q
D.