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K4Q153211M Dataheets PDF



Part Number K4Q153211M
Manufacturers Samsung Semiconductor
Logo Samsung Semiconductor
Description (K4Q153211M / K4Q153212M) 512kx32bit CMOS Quad Casdram
Datasheet K4Q153211M DatasheetK4Q153211M Datasheet (PDF)

www.DataSheet4U.com K4Q153211M, K4Q153212M 512K x 32Bit CMOS Quad CAS DRAM with EDO DESCRIPTION CMOS DRAM This is a 524,288 x 32 bit Extended Data Out CMOS DRAM. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle 1K, access time (-50 or -60), power consumption(Normal or Low power) and SOJ package type are optional features of this family. All of this family have CAS-beforeR.

  K4Q153211M   K4Q153211M


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www.DataSheet4U.com K4Q153211M, K4Q153212M 512K x 32Bit CMOS Quad CAS DRAM with EDO DESCRIPTION CMOS DRAM This is a 524,288 x 32 bit Extended Data Out CMOS DRAM. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle 1K, access time (-50 or -60), power consumption(Normal or Low power) and SOJ package type are optional features of this family. All of this family have CAS-beforeRAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 512Kx32 EDO Mode Quad CAS DRAM is fabricated using Samsung's advanced CMOS process to realize high band-width, low power consumption and high reliability. FEATURES • Part Identification - K4Q153211M-JC (5.0V, 1K Ref.) - K4Q153211M-JL (5.0V, 1K Ref. LP) - K4Q153212M-JC (3.3V, 1K Ref.) - K4Q153212M-JL (3.3V, 1K Ref. LP) • Extended Data Out Mode operation (Fast Page Mode with Extended Data Out) • Four separate CAS pins provide for separate I/O operation • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • Self-refresh capability (L-ver only) • TTL(5V)/LVTTL(3.3V) compatible inputs and outputs • Early Write or output enable controlled write • JEDEC Standard pinout • Plastic SOJ 400mil x 1125mil package • Single +5.0V±0.5V power supply(5V product) • Single +3.3V±0.3V power supply(3.3V product) • Active Power Dissipation Speed -50 -60 3.3V 540 Unit : mW 5.0V 880 825 FUNCTIONAL BLOCK DIAGRAM • Refresh Cycles Part NO. 153211M-J 153212M-J VCC 5.0V 3.3V Refresh cycle 1K 1K Refresh period Normal 16ms 16ms L-ver 128ms 128ms Refresh Timer Refresh Control Row Decoder Sense Amps & I/O RAS CAS0-3 W Control Clocks VBB Generator Vcc Vss CAS0 D/I Buffer CAS0 D/O Buffer CAS1 D/I Buffer CAS1 D/O Buffer OE CAS2 D/I Buffer CAS2 D/O Buffer CAS3 D/I Buffer CAS3 D/O Buffer DQ16 to DQ23 DQ0 to DQ7 DQ8 to DQ15 • Performance Range Speed -50 -60 Refresh Counter tRAC 50ns 60ns tCAC 15ns 17ns tRC 84ns 104ns tHPC 20ns 27ns Remark 5.0V only 5V/3.3V A0 - A9 A0 - A8 Row Address Buffer Col. Address Buffer Memory Array 524,288 x 32 Cells Column Decoder DQ24 to DQ31 SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. www.DataSheet4U.com K4Q153211M, K4Q153212M CMOS DRAM PIN CONFIGURATION (Top Views) VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C VCC DQ8 DQ9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 N.C N.C N.C N.C N.C RAS A0 A1 A2 A3 A4 A5 A6 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23* 24 25 26 27 28 29 30 31 32 33 34 35 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 VSS DQ31 DQ30 DQ29 DQ28 VSS DQ27 DQ26 DQ25 DQ24 N.C VSS DQ23 DQ22 DQ21 DQ20 VSS DQ19 DQ18 DQ17 DQ16 N.C CAS0 CAS1 CAS2 CAS3 W OE N.C N.C N.C A9 A8 A7 VSS Pin Name A0 - A9 DQ0 - 31 RAS CAS0 - 3 W OE VSS VCC N.C Pin Function Address Inputs Data In/Out Row Address Strobe Column Address Strobe Read/Write Input Data Output Enable Ground Power(+5V) Power(+3.3V) No Connection * Pin23 : must be NC or VSS K4Q153211(2)M-J J : 400mil 70pin SOJ www.DataSheet4U.com K4Q153211M, K4Q153212M ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol 3.3V VIN,VOUT VCC Tstg PD IOS Address -0.5 to +4.6 -0.5 to +4.6 -55 to +150 1 50 Rating 5V CMOS DRAM Units -1.0 to +7.0 -1.0 to +7.0 -55 to +150 1 50 V V °C W mA * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol Min VCC VSS VIH VIL 3.0 0 2.2 -0.3*2 3.3V Typ 3.3 0 Max 3.6 0 VCC+0.3*1 0.8 Min 4.5 0 2.4 -1.0*2 5V Typ 5.0 0 Max 5.5 0 VCC+1.0*1 0.8 V V V V Units *1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/15ns(5V), Pulse width is measured at VCC *2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Max Parameter Input Leakage Current (Any input 0≤VIN≤VIN+0.3V, all other input pins not under test=0 Volt) 3.3V Output Leakage Current (Data out is disabled, 0V≤VOUT≤VCC) Output High Voltage Level(IOH=-2mA) Output Low Voltage Level(IOL=2mA) Input Leakage Current (Any input 0≤VIN≤VIN+0.5V, all other input pins not under test=0 Volt) 5V Output Leakage Current (Data out is disabled, 0V≤VOUT≤VCC) Output High Voltage Level(IOH=-5mA) Output Low Voltage Level(IOL=4.2mA) Symbol II(L) IO(L) VOH VOL II(L) IO(L) VOH VOL Min -5 -5 2.4 -5 -5 2.4 Max 5 5 0.4 5 5 0.4 Units.


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