MAX9206

www.DataSheet4U.com 19-2130; Rev 0; 8/01 KIT ATION EVALU ABLE AVAIL 10-Bit Bus LVDS Deserializers Features o Stand-Alone Deserializer (vs. SERDES) Ideal for Unidirectional Links o Automatic Clock Recovery o Allow Hot Insertion and Synchronization Without System Interruption o BLVDS Serial Input Rated for Point-to-Point and Bus Applications o Fast Pseudorandom Lock o Wide Reference Clock Input Range 16MHz to 40MHz (MAX9206) 40MHz to 60MHz (MAX9208) o High 720ps (p-p) Jitter Tolerance (MAX9206) o Low 30mA Supply Current (MAX9206 at 16MHz) o 10-Bit Parallel LVCMOS/LVTTL Output o Up to 600Mbps Throughput (MAX9208) o Programmable Output Strobe Edge o Pin Compatible to DS92LV1212A and DS92LV1224 General Description The MAX9206/MAX9208 deserializers transform a highspeed serial bus low-voltage differential signaling (BLVDS) data stream into 10-bit-wide parallel LVCMOS/ LVTTL data and clock. The deserializers pair with serializers such as the MAX9205/MAX9207, which generate a serial BLVDS signal from 10-bit-wide parallel data. The serializer/deserializer combination reduces interconnect, simplifies PC board layout, and reduces board size. The MAX9206/MAX9208 receive serial data at 400Mbps and 600Mbps, respectively, over board traces or twisted-pair cables. These devices combine frequency lock, bit lock, and frame lock to produce a parallel-rate clock and word-aligned 10-bit data. Serialization eliminates parallel bus clock-to-data and data-to-data skew. A power-down mode reduces t...