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NAND512W4A2C Dataheets PDF



Part Number NAND512W4A2C
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description (NAND512xxA2C) NAND Flash Memories
Datasheet NAND512W4A2C DatasheetNAND512W4A2C Datasheet (PDF)

www.DataSheet4U.com NAND512R3A2C NAND512R4A2C NAND512W3A2C NAND512W4A2C 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories Features ● High density NAND Flash memories – – 512 Mbit memory array Cost effective solutions for mass storage applications x8 or x16 bus width Multiplexed Address/ Data FBGA ● NAND interface – – TSOP48 12 x 20mm ● ● Supply voltage: 1.8V, 3.0V Page size – – x8 device: (512 + 16 spare) Bytes x16 device: (256 + 8 spare) Words x8 device: (16K + 512 spare) Byt.

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www.DataSheet4U.com NAND512R3A2C NAND512R4A2C NAND512W3A2C NAND512W4A2C 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories Features ● High density NAND Flash memories – – 512 Mbit memory array Cost effective solutions for mass storage applications x8 or x16 bus width Multiplexed Address/ Data FBGA ● NAND interface – – TSOP48 12 x 20mm ● ● Supply voltage: 1.8V, 3.0V Page size – – x8 device: (512 + 16 spare) Bytes x16 device: (256 + 8 spare) Words x8 device: (16K + 512 spare) Bytes x16 device: (8K + 256 spare) Words Random access: 12µs (3V)/15µs (1.8V) (max) Sequential access: 30ns (3V)/50ns (1.8V) (min) Page Program time: 200µs (typ) ● ● ● ● Block size – – VFBGA55 8 x 10 x 1mm VFBGA63 9 x 11 x 1mm Hardware Data Protection – Program/Erase locked during Power transitions 100,000 Program/Erase cycles (with ECC) 10 years Data Retention ● Page Read/Program – – – ● Data integrity – – ● ● ● ● ● ● Copy Back Program mode Fast Block Erase: 2ms (Typ) Status Register Electronic Signature Chip Enable ‘don’t care’ Serial Number option Device summary Reference ECOPACK® packages Development tools – – – Error Correction Code models Bad Blocks Management and Wear Leveling algorithms Hardware simulation models Table 1. Part Number NAND512R3A2C NAND512R4A2C(1) NAND512-A2C NAND512W3A2C NAND512W4A2C(1) 1. x16 organization only available for MCP. February 2007 Rev 1 1/51 www.st.com 1 Contents NAND512-A2C Contents 1 2 3 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 Inputs/Outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Inputs/Outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Bus operations . . . . . . . . . . . . . . ..


NAND512W3A2C NAND512W4A2C SHD501603


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